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From WikiChip
Cortex-A75 - Microarchitectures - ARM
< arm holdings
Edit Values | |
Cortex-A75 µarch | |
General Info | |
Arch Type | CPU |
Designer | ARM Holdings |
Manufacturer | TSMC |
Introduction | May 29, 2017 |
Process | 16 nm, 14 nm, 10 nm, 7 nm |
Core Configs | 1, 2 |
Pipeline | |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 11-13 |
Decode | 3-way |
Instructions | |
ISA | ARMv8 |
Extensions | FPU, NEON |
Cache | |
L1I Cache | 8-64 KiB/core 4-way set associative |
L1D Cache | 8-64 KiB/core 4-way set associative |
L2 Cache | 64-256-512 KiB/core |
L3 Cache | 0-4 MiB/Cluster |
Succession | |
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/cortex-a75&oldid=43418"
Facts about "Cortex-A75 - Microarchitectures - ARM"
codename | Cortex-A75 + |
core count | 1 + and 2 + |
designer | ARM Holdings + |
first launched | May 29, 2017 + |
full page name | arm holdings/microarchitectures/cortex-a75 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-A75 + |
pipeline stages (max) | 13 + |
pipeline stages (min) | 11 + |
process | 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) + |