Template:mpu ARMADA 628 was a 32-bit tri-core ARM microprocessor introduced by Marvell in 2011. This processor, which is based on Marvell's Sheeva PJ4 microarchitecture, operated at 1.5 GHz for the 2 "big cores" with lower frequency for the third low-power core. The 628 supported up to 2 GiB of DDR3-1066 memory and integrated a Vivante GC1000 IGP.

Cache

Main article: Sheeva PJ4 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 192 KiB 196,608 B 0.188 MiB L1I$ 96 KiB 98,304 B 0.0938 MiB 3x32 KiB     L1D$ 96 KiB 98,304 B 0.0938 MiB 3x32 KiB     L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     1x1 MiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1066, DDR2-800 Supports ECC No Max Mem 2 GiB Controllers 1 Channels 1 Max Bandwidth 7.942 GiB/s 8,132.608 MiB/s 8.528 GB/s 8,527.658 MB/s 0.00776 TiB/s 0.00853 TB/s Bandwidth Single 7.942 GiB/s

Static Memory Controller

• 4 chip selects, up to 256 MB each
• Asynch/Sync operation up to 78 MHz
• A/D and AA/D Mode, x8 & x16 NOR Flash interface
• Support for VLIO or companion chips

NAND Flash Controller

• ONFI compliant controller supporting SLC and MLC NAND, x8 & x16, small block and large block
• 2 Chip Selects with up to 64GB of address space
• Support for 2 KB and 4 KB page sizes
• 2-bit detect/1-bit correct ECC & 16-bit correct BCH

MMC, SD and SDIO Controller

• 4x MMC/SD/SDIO/CE-ATA Controllers
• Supports MMC/eMMC v4.2, 4.3 and 4.4
• SDIO v 2.0, SDcard v2.1 and v3.0 (UHS-I)
• CE-ATA 1/4/8-Bit, SPI mode and boot suppor

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
	USB Revision 2.0 Ports 3 Features 2x HSIC, 1x FSIC/12pin ULPI UART Ports 4 I²C Ports 6 JTAG Yes

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU GC1000 Designer Vivante Frequency 500 MHz 0.5 GHz 500,000 KHz Output HDMI, DSI Max Resolution HDMI 1920x1080 DSI 1920x1080 Standards DirectX 11 OpenGL 3.0 OpenCL 1.2 OpenGL ES 3.1

• 1080p decode support for H.264 high profile, VC-1/WMV, MPEG-4, MPEG-2, H.263, On-2.
• 1080p encode support for h.264 high profile, MPEG-4, MPEG-2, H.263 and On-2

Hardware Accelerators

Marvell Wireless Trusted Module v3

• Hashing units: MD5, SHA-1, HMAC-SHA-1; SHA-224/SHA256 and HMAC, SHA-512 and HMAC, MD5 and HMAC-MD5
• Symmetric crypto: AES (128 to 256 & ECB, CBC, CTR/XTS modes), DES/3DES (ECB & CBC), RC4
• Asymmetric crypto: ECC (Prime field ECC, FIPS std curve EC-224/256, EC-DSA) & RSA (RSA key gen, PKCS#1 v1.5/v2.1 Digital Signatures, x.509 Digital Certificate), & DiffieHellman Key exchange. True HW RNG, FIPS 140-2 certification

Features

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	VFPv3 Vector Floating Point (VFP) v3 Extension NEON Advanced SIMD extension WMMX Wireless MMX WMMX 2 Wireless MMX 2