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From WikiChip
EPYC - AMD
< amd
| AMD EPYC | |
| |
| EPYC logo | |
| Developer | AMD |
| Manufacturer | GlobalFoundries |
| Type | System on chips |
| Introduction | May 16, 2016 (announced) 2H, 2017 (launch) |
| Architecture | High-performance Server SOCs |
| ISA | x86 |
| µarch | Zen |
| Word size | 64 bit 8 octets
16 nibbles |
| Process | 14 nm 0.014 μm
1.4e-5 mm |
| Technology | CMOS |
| Package | FCLGA-4094 |
| Succession | |
| ← | |
| Opteron | |
EPYC is a family of 64-bit x86 high-performance server multiprocessors introduced in 2017 as the successor to the Opteron family.
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc&oldid=42844"
Facts about "EPYC - AMD"
| designer | AMD + |
| first announced | May 16, 2017 + |
| first launched | June 20, 2017 + |
| full page name | amd/epyc + |
| instance of | system on a chip family + |
| instruction set architecture | x86-64 + |
| main designer | AMD + |
| manufacturer | GlobalFoundries + and TSMC + |
| microarchitecture | Zen +, Zen 2 +, Zen 3 + and Zen 4 + |
| name | AMD EPYC + |
| package | FCLGA-4094 + and FCLGA-? + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |
| socket | Socket SP3 + and Socket SP5 + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |