Template:mpu Core i7-7567U is a 64-bit dual-core high-end performance x86 mobile microprocessor introduced by Intel in early 2017. This processor, which is based on the Kaby Lake microarchitecture, is manufactured on Intel's improved 14nm+ process. The i7-7567U operates at 3.5 GHz with a TDP of 28 W and with a Turbo Boost frequency of 4 GHz for a single active core. This MPU supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory and incorporates Intel's Iris Plus Graphics 650 IGP operating at 300 MHz with a burst frequency of 1.15 GHz. This particular GPU includes an additional 64 MiB of eDRAM L4$.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative write-back L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative write-back L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB 4-way set associative write-back L3$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     2x2 MiB 16-way set associative write-back