Template:mpu Celeron 3965U is a 64-bit dual-core budget x86 mobile microprocessors introduced by Intel in early 2017. The 3965U, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14nm+ process. This processor operates at 2.2 GHz and with a TDP of 15 W and supports up to 32 GiB of dual-channel non-ECC DDR4-2133. Additionally the 3965U incorporates Intel's HD Graphics 610 IGP operating at 300 MHz with a burst frequency of 900 GHz.

Cache

Main article: Kaby Lake § Cache

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Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative write-back L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative write-back L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB 4-way set associative write-back L3$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     2x1 MiB 12-way set associative write-back

Memory controller

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	Integrated Memory Controller
	Max Type LPDDR3-1866, DDR3L-1600, DDR4-2133 Supports ECC No Max Mem 64 GiB Controllers 1 Channels 2 Max Bandwidth 31.79 GiB/s 32,552.96 MiB/s 34.134 GB/s 34,134.253 MB/s 0.031 TiB/s 0.0341 TB/s Bandwidth Single 15.89 GiB/s Double 31.79 GiB/s