From WikiChip
CN5745-800 SP - Cavium
< cavium‎ | octeon plus
Revision as of 00:33, 29 December 2016 by ChipIt (talk | contribs)

Template:mpu CN5745-800 SP is a 64-bit deca-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates ten cnMIPS cores, operates at 800 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon_plus/cn5745-800bg1217-sp&oldid=32280"
Facts about "CN5745-800 SP - Cavium"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN5745-800 SP - Cavium#io +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
l1$ size480 KiB (491,520 B, 0.469 MiB) +
l1d$ size160 KiB (163,840 B, 0.156 MiB) +
l1i$ size320 KiB (327,680 B, 0.313 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
max pcie lanes8 +
supported memory typeDDR2-800 +