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From WikiChip
CN3010-500 CP - Cavium
Template:mpu The CN3010-500 CP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2006. This processor, which incorporates a single cnMIPS core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the CN3005 equivalent as well as support for TDM/PCM (VoIP support).
Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3010-500bg525-cp&oldid=30755"
Facts about "CN3010-500 CP - Cavium"
has ecc memory support | true + |
l1$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) + |
max memory bandwidth | 0.00194 GiB/s (1.986 MiB/s, 0.00208 GB/s, 2.082 MB/s, 1.893997e-6 TiB/s, 2.082472e-6 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR2-533 + |