Template:mpu SC2A11 is a 64-bit tetracosa-core ARM system on a chip designed by Socionext for low-power servers and cloud/IoT edge computing. This chip, which incorporates 24 ultra-low power Cortex-A53 cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.

Cache

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.5 MiB 1,536 KiB 1,572,864 B L1I$ 768 KiB 786,432 B 0.75 MiB 24x32 KiB 2-way set associative   L1D$ 768 KiB 786,432 B 0.75 MiB 24x32 KiB 4-way set associative   L2$ 1.5 MiB 1,536 KiB 1,572,864 B 0.00146 GiB     2x256 KiB 16-way set associative   L3$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2133 Supports ECC Yes Channels 1 Max Bandwidth 15.89 GiB/s 16,271.36 MiB/s 17.062 GB/s 17,061.758 MB/s 0.0155 TiB/s 0.0171 TB/s Bandwidth Single 15.89 GiB/s