Template:mpu Core i5-520M is a 64-bit x86 dual-core mobile microprocessor introduced by Intel in 2010. This processor, which is based on the Westmere microarchitecture (Arrandale core), is manufactured on a 32 nm process. This MPU operates at a base frequency of 2.40 GHz with a Turbo Boost frequency of 2.93 GHz and a TDP of 35 W. This processor incorporated the HD Graphics (Ironlake) IGP on the same package operating at a base frequency of 500.00 MHz and a burst frequency of 766.00 MHz.

Cache

Main article: Westmere § Cache

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Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 4-way set associative write-back L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative write-back L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB 8-way set associative write-back L3$ 3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB     2x1.5 MiB 12-way set associative write-back

Memory controller

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	Integrated Memory Controller
	Max Type DDR3-1066 Supports ECC No Max Mem 8 GiB Controllers 1 Channels 2 Max Bandwidth 15.88 GiB/s 16,261.12 MiB/s 17.051 GB/s 17,051.02 MB/s 0.0155 TiB/s 0.0171 TB/s Bandwidth Single 7.942 GiB/s Double 15.88 GiB/s Physical Address (PAE) 36 bit