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From WikiChip
Cannonlake - Microarchitectures - Intel
< intel | microarchitectures
Edit Values | |
Cannonlake µarch | |
General Info |
Cannonlake (CNL) is a planned microarchitecture by Intel as a successor to Kaby Lake. Cannonlake is expected to be fabricated using a 10 nm process. Cannonlake is set to be introduced in the fourth quarter of 2017.
Process Technology
Cannonlake is set to utilize Intel's 10 nm process (P1274).
This section requires expansion; you can help adding the missing info. |
Codenames
Core | Abbrev | Description | Graphics | Target |
---|---|---|---|---|
Cannonlake Y | CNL-Y | Extremely low power | GT2 | 2-in-1s detachable, tablets, and computer sticks |
Cannonlake U | CNL-U | Ultra-low Power | GT2 | Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
Architecture
This section is empty; you can help add the missing info by editing this page. |
All Cannonlake Chips
Cannonlake Chips | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
Main processor | IGP | ||||||||||
Model | µarch | Platform | Core | Launched | SDP | TDP | Freq | Max Mem | Name | Freq | Max Freq |
Count: 0 |
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