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From WikiChip
AMD-K6-IIIE+/400ACR - AMD
Template:mpu AMD-K6-IIIE+/400ACR is a 32-bit x86 embedded microprocessor designed by AMD and introduced in late 2000. This MPU which was manufactured on a 0.18 µm process, based on K6-III microarchitecture, operated at 400 MHz with a bus of 100 MHz and a multiplier of 4. This chip had a TDP of 9.5 W.
Cache
- Main article: K6-III § Cache
L3$ can be 512 KB to 2 MB, depending on manufacturer and motherboard model. L3$ is off-chip.
Cache Info [Edit Values] | ||
L1I$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
L1D$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
L2$ | 256 KB "KB" is not declared as a valid unit of measurement for this property. |
1x256 4-way set associative (shared) |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
- Halt state
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/k6-iii%2B/amd-k6-iiie%2B-400acr&oldid=24622"
Facts about "AMD-K6-IIIE+/400ACR - AMD"
l1d$ description | 2-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |