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dubious intel statement on scheduler size

According to the Intel presentation slides, they have "Larger out-of-order scheduler" but what's not clear is what they meant by that. The ROB seems to remain at 192 entries. Scheduler is still at 60 entries. Or am I missing something? --At32Hz (talk) 16:20, 14 April 2016 (EDT)

It's increased to 64. I can't find the original Intel source, but its reflected here: https://www.microway.com/knowledge-center-articles/detailed-specifications-of-the-intel-xeon-e5-2600v4-broadwell-ep-processors/ Intel source for the increase in scheduler: https://intel.lanyonevents.com/sz15/connect/fileDownload/session/ECA57E7DBF19B1A610382EB5ABF2B651/SZ15_ARCS001_100_ENGf.pdf slide 21

Also the instruction queue is increased from 2x20 to 2x25, but [citation needed] I guess, can't find it anymore :)