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Am2045 - Ambric
Template:mpu Am2045 (later renamed Am2045A) was Ambric's original flagship MPPA introduced in late 2006. This model was made of 42 Brics arranged as a grid of about 5x9, making up a total of 336 32-bit RICS-like cores operating asynchronously at 1-333 MHz.
Originally this chip was supposed to have 45 Brics, hence the '2045' which was supposed to have 360 cores. However the final model only had 42 bric for 336 cores instead.
Architecture
- Main article: Am2000 § Architecture
The Am2045 is made of 42 homogeneous 'Brics' laid out in a 5 by 9 grid to form 336 cores and 336 RAM units.
General layout:
- 42x Brics
Cache
The Am2045 contains 42 Brics, each with its own RAM Unit (RU) of 13 kB of SRAM for a total of 546 kB of SRAM.
Memory controller
Integrated Memory Controller | |
Type | DDR2-400 |
Controllers | 2 |
Channels | 1 |
Max memory | 4 GB |
Expansions
- PCIe
- JTAG
- 128x GPIO @ 100 MHz
- serial flash
Facts about "Am2045 - Ambric"
base frequency | 333 MHz (0.333 GHz, 333,000 kHz) + |
bus speed | 100 MHz (0.1 GHz, 100,000 kHz) + |
clock multiplier | 3.3 + |
codename | Kestrel + |
core count | 344 + |
designer | Ambric + |
family | Am2000 + |
first announced | October 10, 2006 + |
first launched | January 2007 + |
full page name | ambric/am2000/am2045 + |
has feature | PCIe +, JTAG +, GPIO + and serial flash + |
has locked clock multiplier | false + |
instance of | microprocessor + |
last order | 2012 + |
last shipment | 2012 + |
ldate | January 2007 + |
main image | ![]() |
main image caption | Am2045 + |
market segment | Embedded + |
max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
microarchitecture | Ambric + |
model number | Am2045 + |
name | Am2045 + |
part number | Am2045 + and Am2045A + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
series | Gen 1 + |
technology | CMOS + |
transistor count | 117,000,000 + |
word size | 32 bit (4 octets, 8 nibbles) + |