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From WikiChip
Chaberton-ELP - Microarchitectures - ARM
| Edit Values | |
| Chaberton-ELP µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | 2024 |
| Succession | |
| Contemporary | |
| Chaberton (Cortex-A725) | |
Chaberton-ELP (Cortex-X5) is the successor to the Hunter-ELP (Cortex-X4) and Hunter (Cortex-A720), a performance-enhanced version of the Chaberton (Cortex-A725), low-power high-performance ARM microarchitecture designed by Arm for the mobile market.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/chaberton-elp&oldid=103211"
Facts about "Cortex-X5 (Chaberton-ELP) - Microarchitectures - ARM"
| codename | Chaberton-ELP + |
| designer | ARM Holdings + |
| first launched | 2024 + |
| full page name | arm holdings/microarchitectures/chaberton-elp + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Chaberton-ELP + |