Semiconductor & Computer Engineering
From WikiChip
denver - Nvidia
| Edit Values | |
| Denver µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Nvidia |
| Manufacturer | TSMC |
| Introduction | 2014 |
| Process | 28 nm, 16 nm |
| Core Configs | 2, 4 |
| Pipeline | |
| OoOE | No |
| Decode | 2-way |
| Instructions | |
| ISA | ARMv8 |
| Cache | |
| L1I Cache | 128 KiB/core 4-way set associative |
| L1D Cache | 64 KiB/core 4-way set associative |
| L2 Cache | 2 MiB/core 16-way set associative |
Denver is a CPU microarchitecture from Nvidia introduced in 2014, capable of executing ARMv8 code natively and with help of dynamic code optimization. Native ARM decoder can issue up to 2 instructions per cycle, and up to 7 micro-operations are started per cycle when dynamic code translation is used.
Architecture
Products
Denver is used in Tegra K1-64.
Die
All Denver Chips
| List of all Denver Chips | |||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Main processor | IGP | ||||||||||||||||||||||||
| Model | Launched | Designer | Family | Process | Core | C | T | L2$ | L3$ | Frequency | Max Mem | Designer | Name | Frequency | |||||||||||
| Count: 0 | |||||||||||||||||||||||||
References
- NVIDIA’S FIRST CPU IS A WINNER. Denver Uses Dynamic Translation to Outperform Mobile Rivals. - Linley Gwennap (August 18, 2014)
- IEEE HotChips 26 (HC26), 2014 - Darrell Boggs "Nvidia's Denver Processor"
Facts about "Denver - Microarchitectures - Nvidia"
| codename | Denver + |
| core count | 2 + |
| designer | Nvidia + |
| first launched | 2014 + |
| full page name | nvidia/microarchitectures/denver + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Denver + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) + |