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Core i3-8121U
General Info
Designer	Intel
Manufacturer	Intel
Model Number	i3-8121U
Market	Mobile
Shop	Amazon
General Specs
Family	Core i3
Series	i3-8000
Locked	Yes
Frequency	2,200 MHz
Bus type	OPI
Bus rate	4 GT/s
Clock multiplier	22
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cannon Lake
Core Name	Cannon Lake U
Process	10 nm
Technology	CMOS
Word Size	64 bit
Cores	2
Threads	4
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	15 W
Tstorage	-25 °C – 125 °C
Packaging
Package FCBGA-1356 (BGA) Dimension 42 mm x 24 mm x 1.3 mm Pitch 0.65 mm Ball Count 1356 Ball Comp SAC405 Interconnect BGA-1356

Core i3-8121U is a 64-bit dual-core low-end performance x86 mobile microprocessor introduced by Intel in early 2018. This chip, which is based on the Cannon Lake microarchitecture, is fabricated on Intel's 10 nm process. This processor, which has a base frequency of 2.2 GHz with a TDP of 15 Watts, supports up to 32 GiB of dual-channel DDR4-2400.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Cannon Lake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative write-back L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB 4-way set associative write-back L3$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     2x2 MiB 16-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Supports ECC No Controllers 1 Channels 2 Max Bandwidth 35.76 GiB/s 36,618.24 MiB/s 38.397 GB/s 38,397.008 MB/s 0.0349 TiB/s 0.0384 TB/s Bandwidth Single 17.88 GiB/s Double 35.76 GiB/s

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading EIST Enhanced SpeedStep Technology SST Speed Shift Technology VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) MPX Memory Protection Extensions SGX Software Guard Extensions Secure Key Secure Key Technology SMEP OS Guard Technology Flex Memory Flex Memory Access ISRT Smart Response Technology MWT My WiFi Technology IPT Identity Protection Technology