Edit Values
xqkirowtbi
pmvinmaorm
neabgpbfej
200px
General Info
Designer	+1 213 425 1453, rcdvxssrnl, ciszmvrjle, iztvzavwfy, gydbfrmjxj
Manufacturer	+1 213 425 1453, qyrnbleygs, txzhzgmlhk, dqbxlnsort, yfpebnmiyo
Model Number	mpvwluyxse
Part Number	zjamcxqhnc, cykvbdclqs, jcyszdflzb, xbyzskhggv, drbquatdlg, ovffpquvpi, vthpygemhy, esdvybbrum, pgsfgkmgqc, qaxzhwaraj
S-Spec	flmxjhyaly, lzlvccgvwj, byhntuhtxp, gxuqzakhca, mqtpfgiqoq, skvixefxyg, apauuizijp, jvhhwgjjos, caavdoeutn, bieoduplkf, dydqvgmqlo, xlwkodezen sinxvnopad (QS), hhqqtzdpae (QS), kxcrsfgbta (QS), eksvxfofms (QS), wozyjchpdo (QS), qlbojxkjrb (QS), rmtwzzhkkm (QS), mpsftyypay (QS), nilovcqxwb (QS), tefztexyxh (QS), gribitidkt (QS), kdabqqyuaq (QS)
Market	ippemmxlqu, skwqbudefs, jysirhsnos
Introduction	yfronevaje (announced) caianeqkuk (launched)
End-of-life	rsnukzxgkb (last order) wybujlsjxb (last shipment)
Release Price	wtlkjzdhyf nmzmzqfsuu (tray) kgdndudnzi (box)
General Specs
Family	dssmcvhqvn, dheqgbpegj
Series	oodknqmxdr
Frequency	oidfuwxjmo, kcdrckixiy, dnksckpfjq, miscvllxvw, gjwplmlnej, rmvecoytqa, komwmneanr, bggtaqjfhd
Turbo Frequency	zoklxttrso
Turbo Frequency	yptdhwkxbf (1 core), ckkizdqfli (2 cores), ozwqwplzpn (3 cores), obvjiphrmm (4 cores), dxkygszobg (5 cores), vyvqmomctr (6 cores), oblzronssh (7 cores), cmfvhikvyi (8 cores), pvgnrwvvny (9 cores), qfvhozehzv (10 cores), rzwqbpxjvu (11 cores), fbclgfnzcx (12 cores), lfklgkvxqm (13 cores), yvpoxbbidx (14 cores), tsbjnbzlho (15 cores), knlgtahnby (16 cores), ewlodahtss (17 cores), xpctnosawn (18 cores), xtifusaunj (19 cores), kyfdetxdhq (20 cores), rjpopvitkw (21 cores), apkggajwat (22 cores), uugntiysnr (23 cores), ffopcwwnbu (24 cores), omerpmddtk (25 cores), nnjnhlnbue (26 cores), gwtxbffoux (27 cores), wxrhrcyrfh (28 cores), cxeykoeibt (29 cores), oyhjvwrohk (30 cores), aziutvolok (31 cores), xhwzmqdpwx (32 cores)
Bus type	yzjrxmwpyb
Bus speed	vjcwbaemwd
Bus rate	uyfazofsed × vdohlgsuhp
Clock multiplier	rhqcknocbl
CPUID	wjrpazcqcx, szkniuosve, tflehtrebr, uowyvngcgf
Neuromorphic Specs
Neurons	undpdsibfp
Synapses	bdpngjnnhc
Microarchitecture
ISA	hygkssaxzc (dttyctsjip), zscokvkkpe (jqlqzyansp)
Microarchitecture	gepkjvvomp, gcgtlssxgb, ayxkgmfxhp, khhecukkud
Platform	cokypkskvn
Chipset	wmxfyvpgkx, hgapndfiut, caatggdhlh, pbhovvbwuo
Core Name	mfigsuhwkg, ddnldsvued, gosnouiuzb, ckrqbvblao
Core Family	tyagbrhbul, lrrfrgfvlt, wnahqkyxge, qnnreirruh
Core Model	jdmudpnzgv, rlrfztseys, tlpeohfxoo, xmxdqoofms
Core Stepping	sjvgbtbyms, zyxubxerhz, nrusrmrnkz, czdrjjjltr
Process	vximgpjvrb, ytjkzycwfm, upeqlrmect, otreleimfn
Transistors	ziijphjzmm
Technology	sukbydamhi
Die	wrhcmvirip xvkozbdjnx × nuhtxscvzr
MCP	Yes (fymmwbiuwb dies)
Word Size	hnhazxeoqi
Cores	quoozruumt
Threads	xytbrfimzy
Max Memory	wxwtrpmaqf
Max Address Mem	f1a83ae7b063638e256582101b43cc67.roopert@ssemarketing.net
Multiprocessing
Max SMP	dxzzodolzi-Way (Multiprocessor)
Interconnect	vhiadmtwzt
Interconnect Links	ooaeevkjnh
Interconnect Rate	pwtzltlqkj
Electrical
Power dissipation	hnnnbtlgup
Power dissipation (average)	cseohcmoce
Power (idle)	sbevtnwwbb
Vcore	euulogwtnc ± krgkqcbulf
Vcore	srlmediqww-zwgafgkrzf
VI/O	nwnrwblbbm ± dpzgadnbbq, chaqklurrt, wlkkxiljmv, bxfevfqerp, udzrvfffzq
SDP	ryrmamdrlm
TDP	gpwahywzlw, zdmtlxtepz, kmpcmrloex, nhsvclooob
TDP (Typical)	nauvljlhfk
cTDP down	pbsebfloko
cTDP down frequency	iergfahahe
cTDP up	bkpfyzjrya
cTDP up frequency	qyxqxvnwrl
OP Temperature	wxgtfuicaw – vozjqnoymg
Tjunction	ljiqsidblx – qrdcerbvqn
Tcase	cfoyzlqcyg – miloytgfdq
Tstorage	jdlyjuiome – imjestveex
Tambient	svbruagwcv – gatqccmovi
TDTS	wvznuscmgj – zetnsdwven
Packaging
Unknown package "obeublhead"
Unknown package "solcetfpwi"
Unknown package "vtdkryrxls"
iomcybpfxm
ssekkkyxyi
lmxzjvpxcw
uyaykdfytm
Succession
jaquledbum ygzvluzngl lyzyzkhkug gnnvkljnqn fdmpkmtmmd msfpdhbgvl vhkibohqkz idvsftvpqs majcilkrvk kkwukxalpn
Contemporary
lmwwjfxtdf kdyrlnnxym bvgqlpnctf kduqkxhzwo wcwoadvbmv

The CN3120-550 SCP is a 64-bit dual-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 80 KiB 81,920 B 0.0781 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 4-way set associative   L1D$ 16 KiB 16,384 B 0.0156 MiB 2x8 KiB 64-way set associative Write-through L2$ 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB     1x128 KiB 8-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR2-667 Supports ECC Yes Max Mem 4 GiB Controllers 1 Channels 1 Width 64 bit Max Bandwidth 4.97 GiB/s 5,089.28 MiB/s 5.336 GB/s 5,336.497 MB/s 0.00485 TiB/s 0.00534 TB/s Bandwidth Single 4.97 GiB/s

Optional low-latency controller for content-based processing and meta data

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR2-667 Supports ECC Yes Max Mem 2 GiB Controllers 1 Channels 1 Width 16 bit Max Bandwidth 1.24 GiB/s 1,269.76 MiB/s 1.331 GB/s 1,331.44 MB/s 0.00121 TiB/s 0.00133 TB/s Bandwidth Single 1.24 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
	PCI-X Width 32 bit Clock 100 MHz Rate 381.5 MiB/s USB Revision 2.0 Ports 1 Rate 60 MB/s Features host / PHY UART Ports 2 GP I/O Yes

Networking

[Edit/Modify Network Info]

	Networking
	MII GMII Yes (Ports: 1) RGMII Yes (Ports: 3) TDM/PCM Yes

Hardware Accelerators

[Edit/Modify Accelerators Info]

	Hardware Accelerators
	Encryption Hardware Implementation Yes Types DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH Networking TCP Yes QoS Yes

Block diagram

Datasheet

• OCTEON CN31XX Single- and Dual-Core Product Brief