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Xeon Gold 5118 - Intel
Template:mpu Xeon Gold 5118 is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5118, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 1 AVX-512 FMA unit as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.3 GHz with a TDP of 105 W and a turbo boost frequency of up to 3.2 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Features
[Edit/Modify Supported Features]
Frequencies
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||
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1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | ||
Normal | 2,300 MHz | 3,200 MHz | 3,200 MHz | 3,000 MHz | 3,000 MHz | 2,900 MHz | 2,900 MHz | 2,900 MHz | 2,900 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz |
AVX2 | 1,900 MHz | 3,100 MHz | 3,100 MHz | 2,900 MHz | 2,900 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,300 MHz | 2,300 MHz | 2,300 MHz | 2,300 MHz |
AVX512 | 1,200 MHz | 2,900 MHz | 2,900 MHz | 2,400 MHz | 2,400 MHz | 1,800 MHz | 1,800 MHz | 1,800 MHz | 1,800 MHz | 1,600 MHz | 1,600 MHz | 1,600 MHz | 1,600 MHz |
Benchmarks
Test: SPEC CPU2017
Tested: 2017-09-30 22:55:00-0400
Chips: 2, Cores: 24, Threads: 24
Tested: 2017-09-30 22:55:00-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 5118, 2.30GHz)
System: Cisco UCS B200 M5 (Intel Xeon Gold 5118, 2.30GHz)
SPECspeed2017_fp_base: 1
SPECspeed2017_fp_peak: 82.7
Test: SPEC CPU2017
Tested: 2017-09-30 17:05:03-0400
Chips: 2, Cores: 24, Threads: 24
Tested: 2017-09-30 17:05:03-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 5118, 2.30GHz)
System: Cisco UCS B200 M5 (Intel Xeon Gold 5118, 2.30GHz)
SPECspeed2017_int_base: 1
SPECspeed2017_int_peak: 7.62
Facts about "Xeon Gold 5118 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 5118 - Intel#io +, Xeon Gold 5118 - Intel + and Xeon Gold 5118 - Intel + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
supported memory type | DDR4-2400 + |