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PEZY-SC3
General Info
Designer	PEZY
Manufacturer	TSMC
Model Number	PEZY-SC3
Market	Supercomputer
Introduction	2016 (announced) 2019 (launched)
General Specs
Family	PEZY-SCx
Frequency	1,333 MHz
Microarchitecture
Process	7 nm
Technology	CMOS
Die	700 mm²
Cores	8,096
Threads	65,536
Electrical
Power dissipation	400 W
Vcore	0.65 V

PEZY-SC3 (PEZY Super Computer 3) is a fourth generation many-core microprocessor developed by PEZY set to be introduced in late 2019. This chip, which is planned to operate at 1.3 GHz, will incorporate 8,192 cores and dissipate 400 W. The PEZY-SC3 will power the ZettaScaler-3.x series of supercomputers.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Overview

The SC3 will be introduced by PEZY along with their third-generation ZettaScaler-3.0 supercomputer series. The SC3 is set to incorporate 8,192 cores along with 8-way SMT support for a total of 65,536 threads, four times as many cores as its predecessor.

Operating at 1.3 GHz, the PEZY-SC3 will have a peak performance of 43.69 TFLOPS (single-precision) and 21.845 TFLOPS (double-precision) while consuming around 400 Watts. The PEZY-SC3 is expected to be manufactured on TSMC's 7 nm process.

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Memory controller

For main memory, the PEZY-SC3 supports 4 channels of 64-bit DDR4-3600 memory with ECC support for a total aggregated bandwidth of 107.3 GiB/s

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-3600 Supports ECC Yes Controllers 4 Channels 4 Width 64 bit Max Bandwidth 107.3 GiB/s 109,875.2 MiB/s 115.212 GB/s 115,212.498 MB/s 0.105 TiB/s 0.115 TB/s Bandwidth Single 26.82 GiB/s Double 53.64 GiB/s Quad 107.3 GiB/s

In addition to main memory bandwidth, the PEZY-SC3 supports Wide-IO with a width of 2,048 bit, twice of the SC2. As with the SC2, the SC3 will use ThruChip Interface (TCI) interfaces in order to communicate with the TCI-DRAM chips. This chip incorporates 8 interfaces, operating at 3 GHz for a bandwidth of 1.525 TB/s per interface for a total aggregated bandwidth of 12.2 TB/s - over 5.8 the bandwidth of its predecessor.

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Memory Wide I/O Rate 3,000 MHz Width 2,048 bit Channels 8 Max Bandwidth 11.18 TiB/s 11,448.32 GiB/s 11,723,079.68 MiB/s 12,292.54 GB/s 12,292,539.999 MB/s 12.293 TB/s

Expansions

With the SC3, PEZY plans to replace the previous PCIe interface with a custom optics interface featuring 128 lanes supporting a bandwidth of 256 GB/s.