Template:mpu PEZY-SC3 (PEZY Super Computer 3) is fourth generation many-core microprocessor planned by PEZY. The SC3 incorporates 8,096 cores, four times as many cores as its predecessor.

Planned to be fabricated on TSMC's 7 nm process, PEZY-SC3 operates at 1.33 GHz and consume around 400 W while delivering performance in the order of 87.2 TFLOPS (HP), 43.6 TFLOPS (SP), and 21.8 TFLOPS (DP).

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-3600 Supports ECC Yes Controllers 4 Channels 4 Max Bandwidth 107.3 GiB/s 109,875.2 MiB/s 115.212 GB/s 115,212.498 MB/s 0.105 TiB/s 0.115 TB/s Bandwidth Quad 107.3 GiB/s

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Memory Wide I/O Rate 2,000 MHz Width 3,072 bit Channels 8 Max Bandwidth 11.18 TiB/s 11,448.32 GiB/s 11,723,079.68 MiB/s 12,292.54 GB/s 12,292,539.999 MB/s 12.293 TB/s

Expansions

With the SC3, PEZY plans to replace the previous PCIe interface with a custom optics interface featuring 128 lanes supporting a bandwidth of 256 GB/s.