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Atom C3508
General Info
Designer	Intel
Manufacturer	Intel
Model Number	C3508
Part Number	HW8076503693501
S-Spec	SR3JX
Market	Server, Embedded
Introduction	August 15, 2017 (announced) August 15, 2017 (launched)
Shop	Amazon
General Specs
Family	Atom
Series	3000
Locked	Yes
Frequency	1,600 MHz
Clock multiplier	16
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Goldmont
Core Name	Denverton
Core Family	6
Core Model	95
Core Stepping	B1
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	4
Threads	4
Max Memory	256 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	11.25 W
Tjunction	0 °C – 100 °C
Tcase	0 °C – 90 °C
Tstorage	-25 °C – 125 °C
Tambient	-40 °C – 85 °C
Packaging
Package FCBGA-1310 (BGA) Dimension 34 mm x 28 mm Ball Count 1310 Ball Comp SAC405 Interconnect BGA-1310

Atom C3508 is a 64-bit quad-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3508, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 1.6 GHz with a TDP of 11.25 W. The C3508 supports up to 256 GiB of dual-channel DDR4-1866 ECC memory. This model is part of Denverton's Internet of Things and eTEMP SKUs which come with integrated QuickAssist Technology and support extended ambient operating temperature (-40 °C to 85 °C).

Cache

Main article: Goldmont § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 224 KiB 229,376 B 0.219 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative write-back L1D$ 96 KiB 98,304 B 0.0938 MiB 4x24 KiB 6-way set associative write-back L2$ 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB     4x2 MiB 16-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3L-1600, DDR4-1866 Supports ECC Yes Max Mem 256 GiB Controllers 1 Channels 2 Max Bandwidth 27.82 GiB/s 28,487.68 MiB/s 29.871 GB/s 29,871.498 MB/s 0.0272 TiB/s 0.0299 TB/s Bandwidth Single 13.91 GiB/s Double 27.82 GiB/s

Expansions

This chip incorporates 8 high-speed I/O (HSIO) lanes that may be configured as any combination of the following:

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 8 Configuration: x8, x4, x2 USB Revision: 3.0 Max Ports: 8 SATA Revision: 3.0 Max Ports: 8 HSIO Max Lanes: 8

Networking

[Edit/Modify Network Info]

	Networking
	Ethernet 2.5GbE Yes (Ports: 4)

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AES AES Encryption Instructions RdRand Hardware RNG SHA SHA Extensions x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute EIST Enhanced SpeedStep Technology VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) MPX Memory Protection Extensions QAT Integrated QuickAssist Technology

• Intel's Integrated QuickAssist Technology supports a rate of up to 5 Gbps.