From WikiChip
Atom C3308 - Intel
Edit Values | |||||||||||
Atom C3308 | |||||||||||
General Info | |||||||||||
Designer | Intel | ||||||||||
Manufacturer | Intel | ||||||||||
Model Number | C3308 | ||||||||||
Part Number | HW8076502639802 | ||||||||||
S-Spec | SR38D | ||||||||||
Market | Server, Embedded | ||||||||||
Introduction | August 15, 2017 (announced) August 15, 2017 (launched) | ||||||||||
Release Price | $32.00 | ||||||||||
Shop | Amazon | ||||||||||
General Specs | |||||||||||
Family | Atom | ||||||||||
Series | 3000 | ||||||||||
Locked | Yes | ||||||||||
Frequency | 1,600 MHz | ||||||||||
Turbo Frequency | 2,100 MHz (1 core) | ||||||||||
Clock multiplier | 16 | ||||||||||
Microarchitecture | |||||||||||
ISA | x86-64 (x86) | ||||||||||
Microarchitecture | Goldmont | ||||||||||
Core Name | Denverton | ||||||||||
Core Family | 6 | ||||||||||
Core Model | 95 | ||||||||||
Core Stepping | B1 | ||||||||||
Process | 14 nm | ||||||||||
Technology | CMOS | ||||||||||
Word Size | 64 bit | ||||||||||
Cores | 2 | ||||||||||
Threads | 2 | ||||||||||
Max Memory | 128 GiB | ||||||||||
Multiprocessing | |||||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||||
Electrical | |||||||||||
TDP | 9.5 W | ||||||||||
Tjunction | 0 °C – 100 °C | ||||||||||
Tcase | 0 °C – 89 °C | ||||||||||
Tstorage | -25 °C – 125 °C | ||||||||||
Tambient | -40 °C – 85 °C | ||||||||||
Packaging | |||||||||||
|
Atom C3308 is a 64-bit dual-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3308, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 1.6 GHz with a TDP of 9.5 W and a turbo boost frequency of up to 2.1 GHz. The C3308 supports up to 128 GiB of single channel DDR4-1866 ECC memory. This model is part of Denverton's Internet of Things and eTEMP SKUs which come with integrated QuickAssist Technology and support extended ambient operating temperature (-40 °C to 85 °C).
Cache
- Main article: Goldmont § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||||
|
Expansions
This chip incorporates 6 high-speed I/O (HSIO) lanes that may be configured as any combination of the following:
Expansion Options |
|||||||||||||
|
Networking
Networking
|
||||
|
Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
||||||||||||||||||||||||||||||||||||||||||||||||||||
|
- Intel's Integrated QuickAssist Technology supports a rate of up to 5 Gbps.
Facts about "Atom C3308 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Atom C3308 - Intel#pcie + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Encryption Standard Instruction Set Extension +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions + and Integrated QuickAssist Technology + |
has integrated intel quickassist technology | true + |
has intel enhanced speedstep technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 112 KiB (114,688 B, 0.109 MiB) + |
l1d$ description | 6-way set associative + |
l1d$ size | 48 KiB (49,152 B, 0.0469 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
max hsio lanes | 6 + |
max memory bandwidth | 13.91 GiB/s (14,243.84 MiB/s, 14.936 GB/s, 14,935.749 MB/s, 0.0136 TiB/s, 0.0149 TB/s) + |
max memory channels | 1 + |
max sata ports | 6 + |
max usb ports | 8 + |
part of | Internet of Things and eTEMP SKUs + |
supported memory type | DDR3L-1600 + and DDR4-1866 + |
x86/has memory protection extensions | true + |