Template:mpu R-Car M2 is a mid-range performance embedded tri-core SoC designed by Renesas for the automotive industry and introduced in late 2013. The M2 incorporates two Cortex-A15 cores operating at 1.5 GHz and a third SH-4A core for real-time processing. This chip incorporates Imagination's PowerVR SGX544 GPU operating at 520 MHz and supports up to dual-channel DDR3-1600 memory.

Cache

Main article: Cortex-A15 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 192 KiB 196,608 B 0.188 MiB L1I$ 96 KiB 98,304 B 0.0938 MiB 3x32 KiB     L1D$ 96 KiB 98,304 B 0.0938 MiB 3x32 KiB     L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     1x2 MiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1600 Supports ECC No Controllers 1 Channels 2 Width 32 bit Max Bandwidth 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s Bandwidth Single 5.96 GiB/s Double 11.92 GiB/s

Expansions

• Flash ROM and SRAM, Data bus width: 8 or 16 bits
• PCI Express2.0 (1 lane)
• USB 3.0 host interface × 1 port (wPHY)
• USB 2.0 host interface × 2 ports (wPHY)
• SD host interface × 3 ch (SDXC, UHS-I)
• Multimedia card interface × 1 ch
• Serial ATA interface × 2 ch
• I²C bus interface × 9 ch
• Serial communication interface (SCIF) × 18 ch
• Quad serial peripheral interface (QSPI) × 1 ch (for boot)
• Clock-synchronized serial interface (MSIOF) × 3 ch (SPI/IIS)
• Ethernet AVB controller (IEEE802.1BA/802.1AS/802.1Qav/IEEE1722, GMII/MII, without PHY)
• Ethernet controller (IEEE802.3u, RMII, without PHY)

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU PowerVR SGX544 Designer Imagination Technologies Execution Units 2 Max Displays 2 Frequency 520 MHz 0.52 GHz 520,000 KHz

Features

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	Thumb-2 Thumb-2 Extension ThumbEE Thumb Execution Environment Extension VFPv4 Vector Floating Point (VFP) v4 Extension NEON Advanced SIMD extension

Block Diagram

Dev Board ("KOELSCH")

• 210 mm x 180 mm
• R-Car M2
• 68 MiB serial flash memory
• 2 GiB DDR3-DRAM-1600; 2x 32-bit configuration
• RS-232C, UART, USB, SD, LAN, SATA, PCIe, CAN, MLB interfaces (partially via connector)
• HDMI and LVDS display-out
• switches, LEDs, I/O expansion headers