Template:mpu R-Car L1 is a performance embedded SoC for the automotive industry designed by Renesas. The L1 features a single Cortex-A9 core operating at 400 MHz. This chip incorporates Imagination's PowerVR SGX531 GPU. This SoC supports up to 1 GiB of DDR3-1066 memory.

• Note: It's unknown if this model was ever actually released.

Cache

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 64 KiB 65,536 B 0.0625 MiB L1I$ 32 KiB 32,768 B 0.0313 MiB 1x32 KiB 4-way set associative   L1D$ 32 KiB 32,768 B 0.0313 MiB 1x32 KiB 4-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1066, DDR2-533 Supports ECC No Max Mem 1 GiB Controllers 1 Channels 1 Width 32 bit Max Bandwidth 1.99 GiB/s 2,037.76 MiB/s 2.137 GB/s 2,136.746 MB/s 0.00194 TiB/s 0.00214 TB/s Bandwidth Single 1.99 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU PowerVR SGX531 Designer Imagination Technologies Execution Units 1 Standards OpenGL ES 2.0

Features

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	Thumb-2 Thumb-2 Extension ThumbEE Thumb Execution Environment Extension VFPv3 Vector Floating Point (VFP) v3 Extension NEON Advanced SIMD extension Jazelle Direct Bytecode eXecution