From WikiChip
Atom N280 - Intel
Template:mpu Atom N280 is an ultra-low power 32-bit x86 single-core microprocessor introduced by Intel in early 2009. The N280 is specifically designed for nettops and various other mobile internet connected devices. This processors, which was fabricated on Intel's 45 nm process, was based on the Bonnell microarchitecture. The Atom N280 operates at 1.66 GHz with a TDP of 2.5 W. The MPU features a legacy 667 MT/s front-side bus. This specific model has a faster bus speed vs all other Diamondville models (operating at 166.66 MHz).
Contents
Cache
- Main article: Bonnell § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||
|
Memory controller
This processor has no integrated memory controller.
Graphics
This processor has no integrated graphics.
Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
||||||||||||||||||||||||||||||
|
Facts about "Atom N280 - Intel"
has feature | Hyper-Threading Technology + and Enhanced SpeedStep Technology + |
has intel enhanced speedstep technology | true + |
has simultaneous multithreading | true + |
l1$ size | 56 KiB (57,344 B, 0.0547 MiB) + |
l1d$ description | 6-way set associative + |
l1d$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |