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    CN5740-900 SP  - Cavium    
                	
														Template:mpu CN5740-900 SP is a 64-bit octa-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates eight cnMIPS cores, operates at 900 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.
Contents
Cache
- Main article: cnMIPS § Cache
|  | Cache Organization  Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. | ||||||||||||||||||||||||
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Memory controller
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Expansions
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Networking
Interface options:
- 8-lanes PCIe + 8-lanes PCIe
- 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
- 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
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Hardware Accelerators
[Edit/Modify Accelerators Info]
|  | Hardware Accelerators | |||||||||||||||||
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Block diagram
Datasheet
Facts about "CN5740-900 SP  - Cavium"

