Template:mpu CN5850-600 SCP is a 64-bit dodeca-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 600 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration.

Cache

Main article: cnMIPS § Cache

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Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 576 KiB 589,824 B 0.563 MiB L1I$ 384 KiB 393,216 B 0.375 MiB 12x32 KiB 64-way set associative   L1D$ 192 KiB 196,608 B 0.188 MiB 12x16 KiB 64-way set associative   L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     1x2 MiB 8-way set associative

Memory controller

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	Integrated Memory Controller
	Max Type DDR2-800 Supports ECC Yes Controllers 1 Channels 1 Width 128 bit Max Bandwidth 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s Bandwidth Single 11.92 GiB/s

Expansions

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	Expansion Options
	PCI-X Width 64 bit Clock 133.33 MHz Rate 1,017.25 MiB/s Features host or slave UART Ports 2 GP I/O Yes

Networking

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	Networking
	MII RGMII Yes (Ports: 8) SPI SPI-4.2 Yes (Ports: 2)

Hardware Accelerators

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	Hardware Accelerators
	Encryption Hardware Implementation Yes Types DES, 3DES, AES-GCM, AES up to 256, SHA1, SHA-2 up to SHA-512, RSA up to 8192, DH, KASUMI Networking TCP Yes QoS Yes