Template:mpu
The CN3850-400 EXP is a 64-bit dodeca-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates twelve cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Cache
- Main article: cnMIPS § Cache
[Edit/Modify Cache Info]
|  | Cache Organization  Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU  by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes  and mebibytes . | 
| | L1$ | 480 KiB 491,520 B 0.469 MiB
 
 | | L1I$ | 384 KiB 393,216 B 0.375 MiB
 
 | 12x32 KiB | 64-way set associative |  | 
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 | L1D$ | 96 KiB 98,304 B 0.0938 MiB
 
 | 12x8 KiB | 64-way set associative | Write-through | 
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 | 
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 | 
 |  | L2$ | 1 MiB 1,024 KiB 1,048,576 B
 9.765625e-4 GiB
 
 | |  |  | 1x1 MiB | 8-way set associative |  | 
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Memory controller
[Edit/Modify Memory Info]
|  | Integrated Memory Controller | 
| | Max Type | DDR2-800 | 
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 | Supports ECC | Yes | 
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 | Max Mem | 16 GiB | 
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 | Controllers | 1 | 
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 | Channels | 1 | 
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 | Width | 128 bit | 
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 | Max Bandwidth | 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s
 12,799.003 MB/s
 0.0116 TiB/s
 0.0128 TB/s
 
 | 
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 | Bandwidth | Single 11.92 GiB/s | 
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 | 
 
Expansions
Networking
Hardware Accelerators
Block diagram
 
Datasheet