Template:mpu Xeon E7-8850 is a 64-bit deca-core x86 data center microprocessor that supports up to 8 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2 GHz with turob frequency of 2.4 GHz for 2 active cores. This chip has a TDP of 130 W, supporting up to 4 channels of DDR3 with support of up to 4 TB of memory.

Cache

Main article: Westmere § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 640 KiB 655,360 B 0.625 MiB L1I$ 320 KiB 327,680 B 0.313 MiB 10x32 KiB 4-way set associative write-back L1D$ 320 KiB 327,680 B 0.313 MiB 10x32 KiB 8-way set associative write-back L2$ 2.56 MiB 2,621.44 KiB 2,684,354.56 B 0.0025 GiB     10x256 KiB 8-way set associative write-back L3$ 24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB     10x2.4 MiB 16-way set associative write-back

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1066 Supports ECC Yes Max Mem 4 TiB Controllers 1 Channels 4 Max Bandwidth 31.77 GiB/s 32,532.48 MiB/s 34.113 GB/s 34,112.778 MB/s 0.031 TiB/s 0.0341 TB/s Bandwidth Single 7.942 GiB/s Double 15.88 GiB/s Triple 23.83 GiB/s Quad 31.77 GiB/s Physical Address (PAE) 44 bit