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MSM6500 - Qualcomm
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Template:mpu MSM6500 is a 32-bit ARM system-on-chip with 3G wireless capabilities developed by Qualcomm and introduced in 2003 for the mobile market. This SoC was part of the MSM6xxx Multimedia Platform offering support for more advanced features such as position-location services, video, audio, and gaming.

Cache

Main article: ARM9 § Cache
Cache Info [Edit Values]
L1I$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 4-way set associative
L1D$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 4-way set associative

Wireless

Antu network-wireless-connected-100.svgWireless Communications
Cellular
2G
GSM Yes
GPRS Yes
cdmaOne
IS-95AYes
IS-95BYes
3G
CDMA2000
1XYes
1xEV-DOYes
Retrieved from "https://en.wikichip.org/w/index.php?title=qualcomm/msm6xxx/msm6500&oldid=28436"
Facts about "MSM6500 - Qualcomm"
RDF feed
base frequency146 MHz (0.146 GHz, 146,000 kHz) +
bus typeAMBA 2 +
chipsetMSM6xxx +
core count1 +
core nameARM926EJ-S +
designerQualcomm + and ARM Holdings +
dspQDSP4000 +
dsp base frequency73 MHz (0.073 GHz, 73,000 kHz) +
familyMSM6xxx +
first announcedMarch 20, 2001 +
first launchedJuly 9, 2003 +
full page namequalcomm/msm6xxx/msm6500 +
has 2g supporttrue +
has 3g supporttrue +
has cdma2000 1x supporttrue +
has cdma2000 1xev-do supporttrue +
has cdma2000 supporttrue +
has cdmaone supporttrue +
has gprs supporttrue +
has gsm supporttrue +
has is-95a supporttrue +
has is-95b supporttrue +
has locked clock multipliertrue +
instance ofmicroprocessor +
l1d$ description4-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
ldateJuly 9, 2003 +
main imageFile:msm6500 hires.jpg +
manufacturerTSMC + and IBM +
market segmentMobile + and Embedded +
max cpu count1 +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory address0xFFFFFFFF +
microarchitectureARM9 +
model numberMSM6500 +
nameQualcomm MSM6500 +
part ofMultimedia Platform +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesMSM +
smp max ways1 +
technologyCMOS +
thread count1 +