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From WikiChip
					
    Duron 1000 (Camaro)  - AMD    
                	
														Template:mpu The Mobile Duron 1000 based on the Morgan (Camaro) core was a 32-bit x86 microprocessor developed by AMD and introduced in late 2001. This model was part of the second generation of the Duron family. Designed based on AMD's K7 on a 180 nm process, this MPU operated at 1000 MHz with a bus capable of 200 MT/s with a max TDP of 25 W.
Cache
- Main article: K7 § Cache
 
| Cache Info [Edit Values] | ||
| L1I$ |  64 KiB 65,536 B   0.0625 MiB  | 
1x64 KiB 2-way set associative | 
| L1D$ |   64 KiB 65,536 B   0.0625 MiB  | 
1x64 KiB 2-way set associative | 
| L2$ |   64 KiB 0.0625 MiB   65,536 B 6.103516e-5 GiB  | 
1x64 KiB 16-way set associative | 
Graphics
This SoC has no integrated graphics processing unit.
Features
- Halt State
 - Sleep State
 
Documents
DataSheet
- Mobile AMD Duron Processor Model 7 Data Sheet; Publication # 24068; Rev: F; Issue Date: December 2001.
 
See also
Facts about "Duron 1000 (Camaro)  - AMD"
| has feature | Halt State + and Sleep State + | 
| l1d$ description | 2-way set associative + | 
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + | 
| l1i$ description | 2-way set associative + | 
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + | 
| l2$ description | 16-way set associative + | 
| l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |