Template:mpu PEZY-SCnp (SC - Super Computer; np - New Package) is a revised version of the PEZY-SC model by PEZY introduced in may of 2016. The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. The PEZY-SCnp is said to deliver 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. As with the PEZY-SC, the SCnp is also manufactured on TSMC's 28HPC+ (28 nm process).

Architecture

Main article: PEZY-SC §Architecture

The PEZY-SCnp's architecture is identical to the PEZY-SC.

Cache

PEZY-SC's cache is separate from the ARM926's cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared).

Cache Info [Edit Values]
L1I$	2 MiB 2,048 KiB 2,097,152 B	1024x2 KiB (per processor element)
L1D$	1 MiB 1,024 KiB 1,048,576 B	512x2 KiB (per 2 processor elements)
L2$	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	4x2 MiB (per city)
L3$	8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB	4x2 MiB (per prefecture)

Memory controller

Integrated Memory Controller
Type	DDR4-1866
Controllers	1
Channels	8
Bandwidth (single)	14,933 MB/s
Bandwidth (dual)	29,866 MB/s
Bandwidth (quad)	59,732 MB/s
Bandwidth (octa)	119,464 MB/s