From WikiChip
Core i3-6120T - Intel
< intel‎ | core i3
Revision as of 15:21, 9 December 2016 by David (talk | contribs)

Template:mpu Core i3-6120T is a 64-bit dual-core low-end performance microprocessor set to be introduced by Intel in 2016.



DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core, write-back)
L1D$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core, write-back)
L2$ 512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
2x256 KiB 4-way set associative (per core, write-back)
L3$ 3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
shared

Expansions

Template:mpu expansions

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i3/6120t&oldid=31145"
Facts about "Core i3-6120T - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ descriptionshared +
l3$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +