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From WikiChip
AMD-K6-III+/500ACZ - AMD
Template:mpu AMD-K6-III+/500ACZ is a 32-bit x86 mobile microprocessor designed by AMD and introduced in early 2000. This MPU which was manufactured on a 0.18 µm process, based on K6-III microarchitecture, operated at 500 MHz with a bus of 100 MHz and a multiplier of 5 with a maximum power dissipation rating of 16 W and a typical rating of 12.6 W.
Cache
- Main article: K6-III § Cache
L3$ can be 512 KB to 2 MB, depending on manufacturer and motherboard model. L3$ is off-chip.
Cache Info [Edit Values] | ||
L1I$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
L1D$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
L2$ | 256 KB "KB" is not declared as a valid unit of measurement for this property. |
1x256 4-way set associative (shared) |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
- Halt state
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/k6-iii%2B/amd-k6-iii%2B-500acz&oldid=24597"
Facts about "AMD-K6-III+/500ACZ - AMD"
l1d$ description | 2-way set associative + |
l1i$ description | 2-way set associative + |
l2$ description | 4-way set associative + |