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Difference between revisions of "intel/microarchitectures/gracemont"
< intel‎ | microarchitectures

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{{intel title|Gracemont|arch}}
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S
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{{microarchitecture
 
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|atype=CPU
 
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|name=Gracemont
 
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|designer=Intel
 
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|manufacturer=Intel
 
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|introduction=2021
 
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|process=10 nm
 
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|type=Superscalar
 
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|oooe=Yes
 
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|speculative=Yes
 
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|renaming=Yes
 
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|isa=x86-64
 
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|extension=MOVBE
 
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|extension 2=MMX
 
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|extension 3=SSE
 
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|extension 4=SSE2
 
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|extension 5=SSE3
 
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|extension 6=SSSE3
 
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|extension 7=SSE4.1
 
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|extension 8=SSE4.2
 
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|extension 9=POPCNT
 
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|extension 10=AES
 
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|extension 11=PCLMUL
 
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|extension 12=RDRND
 
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|extension 13=XSAVE
 
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|extension 14=XSAVEOPT
 
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|extension 15=FSGSBASE
 
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|extension 16=PTWRITE
 
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|extension 17=RDPID
 
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|extension 18=SGX
 
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|extension 19=UMIP
 
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|extension 20=GFNI-SSE
 
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|extension 21=CLWB
 
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|extension 22=ENCLV
 
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|extension 23=SHA
 
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|core name=
 
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|core name 2=
 
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|core name 3=
 
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|predecessor=Tremont
 
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|predecessor link=intel/microarchitectures/tremont
 
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}}
 
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'''Gracemont''' is [[Intel]]'s successor to {{\\|Tremont}}, a [[10 nm]] microarchitecture for ultra-low power devices and microservers.
 
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== Process Technology ==
 
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Gracemont is designed to take advantage of Intel's [[10 nm process]].
 
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== Architecture ==
 
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=== Key changes from {{\\|Tremont}}===
 
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{{future information}}
 

Revision as of 17:47, 23 March 2020

S

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Facts about "Gracemont - Microarchitectures - Intel"
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codenameGracemont +
designerIntel +
first launched2021 +
full page nameintel/microarchitectures/gracemont +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameGracemont +
process10 nm (0.01 μm, 1.0e-5 mm) +