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| − | {{intel title|Ice Lake (server)|arch}}
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| − | {{microarchitecture
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| − | |atype=CPU
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| − | |name=Ice Lake (server)
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| − | |designer=Intel
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| − | |manufacturer=Intel
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| − | |introduction=2020
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| − | |process=10 nm
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| − | |isa=x86-64
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| − | |core name=Ice Lake SP
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| − | |core name 2=Ice Lake X
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| − | |predecessor=Cooper Lake
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| − | |predecessor link=intel/microarchitectures/cooper lake
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| − | |successor=Sapphire Rapids
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| − | |successor link=intel/microarchitectures/sapphire rapids
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| − | |contemporary=Ice Lake (client)
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| − | |contemporary link=intel/microarchitectures/ice_lake_(client)
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| − | }}
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| − | '''Ice Lake''' ('''ICL''', '''ICX''') '''Server Configuration''' is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[10 nm]] [[microarchitecture]] for enthusiasts and servers.
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| | | | |
| − | == Codenames ==
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| − | {| class="wikitable"
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| − | |-
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| − | ! Core !! Abbrev !! Target
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| − | |-
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| − | | {{intel|Ice Lake X|l=core}} || ICL-X || High-end desktops & enthusiasts market
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| − | |-
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| − | | {{intel|Ice Lake W|l=core}} || ICL-W || Enterprise/Business workstations
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| − | |-
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| − | | {{intel|Ice Lake SP|l=core}} || ICL-SP || Server Scalable Processors
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| − | |}
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| − |
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| − | == Release Dates ==
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| − | [[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|{{\\|Cooper Lake}} and Ice Lake roadmap.]]
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| − | Ice Lake server processors are said to launch in the first half of 2020.
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| − |
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| − | == Process Technology==
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| − | {{see also|intel/microarchitectures/ice lake (client)#Process_Technology|l1=Ice Lake (client) § Process Technology}}
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| − | Ice Lake will use a second-generation enhanced [[10 nm process]] called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.
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| − |
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| − | == Compiler support ==
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| − | Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.
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| − | {| class="wikitable"
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| − | |-
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| − | ! Compiler !! Arch-Specific || Arch-Favorable
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| − | |-
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| − | | [[ICC]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code>
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| − | |-
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| − | | [[GCC]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code>
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| − | |-
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| − | | [[LLVM]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code>
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| − | |-
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| − | | [[Visual Studio]] || <code>/?</code> || <code>/tune:?</code>
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| − | |}
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| − |
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| − | === CPUID ===
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| − | {| class="wikitable tc1 tc2 tc3 tc4"
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| − | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
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| − | |-
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| − | | rowspan="2" | ? || 0 || 0x6 || 0x? || ?
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| − | |-
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| − | | colspan="4" | Family 6 Model ?
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| − | |-
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| − | | rowspan="2" | ? || 0 || 0x6 || ? || ?
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| − | |-
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| − | | colspan="4" | Family 6 Model ?
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| − | |}
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| − |
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| − | == Architecture ==
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| − |
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| − | === Key changes from {{\\|Cascade Lake}}===
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| − | * Enhanced "10nm+" (from [[14 nm]])
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| − | * {{\\|Sunny Cove|Sunny Cove core}}
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| − | ** ''See {{\\|Sunny Cove}} for microarchitectural details and changes''
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| − | * I/O
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| − | ** PCIe 4.0 (from PCIe 3.0)
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| − | * Memory
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| − | ** Higher bandwidth (190.7 GiB/s, up from 143.1 GiB/s)
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| − | ** Octa-channel (up from hexa-channel)
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| − | ** 3200 MT/s (up from 2933 MT/s)
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| − | ** Optane DC DIMMs
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| − | *** Apache Pass '''→''' Barlow Pass
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| − | * Platform
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| − | ** {{intel|Purley|l=platform}} '''→''' {{intel|Whitley|l=platform}}
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| − | * Packaging
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| − | ** 4189-contact flip-chip LGA (up from 3647 contacts)
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| − | {{expand list}}
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| − |
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| − | ====New instructions ====
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| − | Ice Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|Sunny cove#New instructions|Sunny Cove § New Instructions|l=arch}} for details.
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| − |
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| − | == All Ice Lake Chips ==
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| − | {{future information}}
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| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − |
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| − | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc6 tc7 tc14 tc15">
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| − | <tr class="comptable-header"><th> </th><th colspan="24">List of Ice Lake Processors</th></tr>
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| − | <tr class="comptable-header"><th> </th><th colspan="9">Main processor</th><th colspan="2">Frequency/{{intel|Turbo Boost|Turbo}}</th><th>Mem</th><th colspan="7">Major Feature Diff</th></tr>
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| − | {{comp table header 1|cols=Launched, Price, Family, Core Name, Cores, Threads, %L2$, %L3$, TDP, %Frequency, %Max Turbo, Max Mem, Turbo, SMT}}
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| − | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Uniprocessors]]</th></tr>
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| − | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]] [[max cpu count::1]]
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| − | |?full page name
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| − | |?model number
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| − | |?first launched
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| − | |?release price
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| − | |?microprocessor family
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| − | |?core name
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| − | |?core count
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| − | |?thread count
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| − | |?l2$ size
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| − | |?l3$ size
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| − | |?tdp
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| − | |?base frequency#GHz
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| − | |?turbo frequency (1 core)#GHz
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| − | |?max memory#GiB
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| − | |?has intel turbo boost technology 2_0
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| − | |?has simultaneous multithreading
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| − | |format=template
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| − | |template=proc table 3
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| − | |searchlabel=
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| − | |sort=microprocessor family, model number
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| − | |order=asc,asc
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| − | |userparam=16:15
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| − | |mainlabel=-
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| − | |limit=200
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| − | }}
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| − | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Multiprocessors]] (2-way)</th></tr>
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| − | {{#ask:
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| − | [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]] [[max cpu count::2]]
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| − | |?full page name
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| − | |?model number
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| − | |?first launched
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| − | |?release price
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| − | |?microprocessor family
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| − | |?core name
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| − | |?core count
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| − | |?thread count
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| − | |?l2$ size
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| − | |?l3$ size
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| − | |?tdp
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| − | |?base frequency#GHz
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| − | |?turbo frequency (1 core)#GHz
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| − | |?max memory#GiB
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| − | |?has intel turbo boost technology 2_0
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| − | |?has simultaneous multithreading
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| − | |format=template
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| − | |template=proc table 3
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| − | |searchlabel=
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| − | |sort=microprocessor family, model number
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| − | |order=asc,asc
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| − | |userparam=16:15
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| − | |mainlabel=-
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| − | |limit=60
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| − | }}
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| − | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Multiprocessors]] (4-way)</th></tr>
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| − | {{#ask:
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| − | [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]] [[max cpu count::4]]
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| − | |?full page name
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| − | |?model number
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| − | |?first launched
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| − | |?release price
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| − | |?microprocessor family
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| − | |?core name
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| − | |?core count
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| − | |?thread count
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| − | |?l2$ size
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| − | |?l3$ size
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| − | |?tdp
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| − | |?base frequency#GHz
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| − | |?turbo frequency (1 core)#GHz
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| − | |?max memory#GiB
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| − | |?has intel turbo boost technology 2_0
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| − | |?has simultaneous multithreading
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| − | |format=template
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| − | |template=proc table 3
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| − | |searchlabel=
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| − | |sort=microprocessor family, model number
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| − | |order=asc,asc
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| − | |userparam=16:15
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| − | |mainlabel=-
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| − | |limit=60
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| − | }}
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| − | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Multiprocessors]] (8-way)</th></tr>
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| − | {{#ask:
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| − | [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]] [[max cpu count::8]]
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| − | |?full page name
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| − | |?model number
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| − | |?first launched
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| − | |?release price
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| − | |?microprocessor family
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| − | |?core name
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| − | |?core count
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| − | |?thread count
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| − | |?l2$ size
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| − | |?l3$ size
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| − | |?tdp
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| − | |?base frequency#GHz
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| − | |?turbo frequency (1 core)#GHz
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| − | |?max memory#GiB
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| − | |?has intel turbo boost technology 2_0
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| − | |?has simultaneous multithreading
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| − | |format=template
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| − | |template=proc table 3
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| − | |searchlabel=
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| − | |sort=microprocessor family, model number
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| − | |order=asc,asc
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| − | |userparam=16:15
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| − | |mainlabel=-
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| − | |limit=60
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| − | }}
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| − | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]]}}
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| − | </table>
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| − | {{comp table end}}
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