Semiconductor & Computer Engineering
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Difference between revisions of "cea-leti/microarchitectures/tsarlet"
(cea leti soc) |
m (David moved page cea-leti/96-core 6-chiplet mips processor to cea-leti/tsarlet without leaving a redirect: CEA told me there's a name for it...) |
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Revision as of 01:05, 29 February 2020
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96-Core 6-Chiplet 3D stacked MIPS processor (no actual name was given to the project) was a large-scale high-performance SoC technology demonstration by CEA-Leti. The project comprised 96 MIPS cores built using 6 chiplets 3D stack on an active interposer in order to demonstarte in-package silicon scale-out capabilities with superior inter-chip capabilities while reducing the overall power and production cost.
Facts about "TSARLET - Microarchitectures - CEA Leti"
| codename | TSARLET + |
| core count | 96 + |
| designer | CEA-Leti + |
| full page name | cea-leti/microarchitectures/tsarlet + |
| instance of | microarchitecture + |
| instruction set architecture | MIPS32v1 + |
| manufacturer | STMicroelectronics + |
| microarchitecture type | CPU + |
| name | TSARLET + |
| pipeline stages | 5 + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + and 65 nm (0.065 μm, 6.5e-5 mm) + |