Revision as of 12:01, 29 November 2019

Kirin 990 4G is a 64-bit high-performance mobile ARM LTE SoC designed by HiSilicon and introduced in late 2019. Fabricated on TSMC's 7 nm process, the 990 4G incorporates two high frequency Cortex-A76 cores operating at 2.86 GHz along with two medium frequency Cortex-A76 cores operating at 2.09 GHz along with four Cortex-A55 cores operating at up to 1.86 GHz.

This SoC has an integrated LTE modem Balong 765 supporting 1.6 Gbps download (Cat21), incorporates an ARM Mali-G76, and supports LPDDR4X-4266 memory.

Overview

Introduced at the 2019 IFA, the Kirin 990 4G uses the same ARM cortex (Cortex A76 + Cortex A55) versions as its predecessor, the Kirin 980, but the clock frequencies have been increased: The Kirin 990 4G features two high-performance big Cortex-A76 core operating at 2.86 GHz, 2 medium-performance big Cortex-A76 operating at 2.09 GHz, and four little Cortex-A55 cores operating at 1.86 GHz. The Kirin 990 4G has approximately 8.0 billion transistors, compared to 6.9 billions transistors of his precedessor, the Kirin 980, that has been produced in the same 7nm process node at TSMC in Taiwan. The Kirin 990 4G incorporates an in-house developed NPU dual-neural processor "DaVinci" designed for AI acceleration.

Cache

Main articles: Cortex-A55 § Cache and Cortex-A76 § Cache

For the Cortex-A76:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 512 KiB 524,288 B 0.5 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 4x64 KiB     L1D$ 256 KiB 262,144 B 0.25 MiB 4x64 KiB     L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     4x512 KiB

For the Cortex-A55:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB     L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB     L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     4x128 KiB

Memory controller

The Kirin 990 4G supports 4-channel LPDDR4X up to 4266 MHz. Each channel supports at most two ranks.

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4X-4266 Supports ECC No Max Mem 8 GiB Controllers 1 Channels 4 Width 16 bit Max Bandwidth 31.78 GiB/s 32,542.72 MiB/s 34.124 GB/s 34,123.515 MB/s 0.031 TiB/s 0.0341 TB/s Bandwidth Double 15.89 GiB/s Quad 31.78 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Mali-G76 Designer ARM Holdings Execution Units 16 Max Displays 2 Frequency 600 MHz 0.6 GHz 600,000 KHz Output DSI Standards DirectX 12 OpenCL 1.2 OpenGL ES 3.2 OpenVG 1.1 Vulkan 1.0

Wireless

• LTE Modem
  • DL: Up to User Equipment (UE) category 21
    • Downlink of up to 1.6 Gbps (4x4 MIMO + 256QAM 3CC CA = 1.6 Gbps, 2x2 MIMO + 256QAM + 1CC = 200 Mbps)
  • UL: Up to User Equipment (UE) category 19
    • Uplink of up to 200 Mbps (2x2 MIMO, 256-QAM, 1x20MHz CA)
• Wi-Fi 802.11 ac
• Bluetooth 5
• NFC
• GPS / A-GPS / GLONASS / BDS

Utilizing devices

Bibliography

• Huawei Kirin 990 Keynote, 2019 IFA