From WikiChip
Difference between revisions of "intel/core i5/i5-560m"
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|x8664=Yes | |x8664=Yes | ||
|nx=Yes | |nx=Yes | ||
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|mmx=Yes | |mmx=Yes | ||
|emmx=Yes | |emmx=Yes | ||
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|sse42=Yes | |sse42=Yes | ||
|sse4a=No | |sse4a=No | ||
+ | |sse_gfni=No | ||
|avx=No | |avx=No | ||
+ | |avx_gfni=No | ||
|avx2=No | |avx2=No | ||
− | + | |avx512f=No | |
+ | |avx512cd=No | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=No | ||
+ | |avx512dq=No | ||
+ | |avx512vl=No | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx512vnni=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |avx512gfni=No | ||
+ | |avx512vaes=No | ||
+ | |avx512vbmi2=No | ||
+ | |avx512bitalg=No | ||
+ | |avx512vpclmulqdq=No | ||
|abm=No | |abm=No | ||
|tbm=No | |tbm=No | ||
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|clmul=No | |clmul=No | ||
|f16c=No | |f16c=No | ||
+ | |bfloat16=No | ||
|tbt1=Yes | |tbt1=Yes | ||
− | |tbt2= | + | |tbt2=Yes |
− | |tbmt3= | + | |tbmt3=Yes |
− | |bpt= | + | |tvb=Yes |
+ | |bpt=Yes | ||
|eist=Yes | |eist=Yes | ||
+ | |sst=Yes | ||
|flex=Yes | |flex=Yes | ||
|fastmem=Yes | |fastmem=Yes | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=Yes | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
|isrt=No | |isrt=No | ||
+ | |sba=No | ||
|mwt=No | |mwt=No | ||
|sipp=No | |sipp=No | ||
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|securekey=No | |securekey=No | ||
|osguard=No | |osguard=No | ||
+ | |intqat=No | ||
+ | |dlboost=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
|smartmp=No | |smartmp=No | ||
|powernow=No | |powernow=No | ||
+ | |amdvi=No | ||
|amdv=No | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
|rvi=No | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
}} | }} |
Revision as of 12:09, 2 August 2019
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Intel Core i5-560M | ||||||||||||
General Info | ||||||||||||
Designer | Intel | |||||||||||
Manufacturer | Intel | |||||||||||
Model Number | i5-560M | |||||||||||
Part Number | BX80617I5560M, CP80617005487AA, CN80617005487AA | |||||||||||
S-Spec | SLBTS, SLBTT | |||||||||||
Market | Mobile | |||||||||||
Introduction | September 26, 2010 (announced) September 26, 2010 (launched) | |||||||||||
End-of-life | April 05, 2012 (last order) October 08, 2012 (last shipment) | |||||||||||
Release Price | $225 | |||||||||||
Shop | Amazon | |||||||||||
General Specs | ||||||||||||
Family | Core i5 | |||||||||||
Series | i5-500 | |||||||||||
Locked | Yes | |||||||||||
Frequency | 2,666.66 MHz | |||||||||||
Turbo Frequency | Yes | |||||||||||
Turbo Frequency | 3,199.99 MHz (1 core), 2,933.33 MHz (2 cores) | |||||||||||
Bus type | DMI 1.0 | |||||||||||
Bus rate | 1 × 2.5 GT/s | |||||||||||
Clock multiplier | 20 | |||||||||||
CPUID | 0x20655 | |||||||||||
Microarchitecture | ||||||||||||
ISA | x86-64 (x86) | |||||||||||
Microarchitecture | Westmere | |||||||||||
Platform | Calpella | |||||||||||
Chipset | Ibex Peak | |||||||||||
Core Name | Arrandale | |||||||||||
Core Family | 6 | |||||||||||
Core Model | 37 | |||||||||||
Core Stepping | K0 | |||||||||||
Process | 32 nm | |||||||||||
Transistors | 382,000,000 | |||||||||||
Technology | CMOS | |||||||||||
Die | 81 mm² | |||||||||||
Word Size | 64 bit | |||||||||||
Cores | 2 | |||||||||||
Threads | 4 | |||||||||||
Max Memory | 8 GiB | |||||||||||
Multiprocessing | ||||||||||||
Max SMP | 1-Way (Uniprocessor) | |||||||||||
Electrical | ||||||||||||
TDP | 35 W | |||||||||||
Tjunction | 0 °C – 105 °C | |||||||||||
Tstorage | -25 °C – 125 °C | |||||||||||
Packaging | ||||||||||||
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Core i5-560M is a 64-bit x86 dual-core mobile microprocessor introduced by Intel in 2010. This processor, which is based on the Westmere microarchitecture (Arrandale core), is manufactured on a 32 nm process. This MPU operates at a base frequency of 2.66 GHz with a Turbo Boost frequency of 3.20 GHz and a TDP of 35 W. This processor incorporated the HD Graphics (Ironlake) IGP on the same package operating at a base frequency of 500.00 MHz and a burst frequency of 766.00 MHz.
Cache
- Main article: Westmere § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
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Integrated Graphics Information
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Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Core i5-560M - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-560M - Intel#package + and Core i5-560M - Intel#io + |
base frequency | 2,666.66 MHz (2.667 GHz, 2,666,660 kHz) + |
bus links | 1 + |
bus rate | 2,500 MT/s (2.5 GT/s, 2,500,000 kT/s) + |
bus type | DMI 1.0 + |
chipset | Ibex Peak + |
clock multiplier | 20 + |
core count | 2 + |
core family | 6 + |
core model | 37 + |
core name | Arrandale + |
core stepping | K0 + |
cpuid | 0x20655 + |
designer | Intel + |
device id | 0x0046 + |
die area | 81 mm² (0.126 in², 0.81 cm², 81,000,000 µm²) + |
family | Core i5 + |
first announced | September 26, 2010 + |
first launched | September 26, 2010 + |
full page name | intel/core i5/i5-560m + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 1.0 +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Flex Memory Access +, Enhanced SpeedStep Technology + and Extended Page Tables + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 1 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | HD Graphics (Ironlake) + |
integrated gpu base frequency | 500 MHz (0.5 GHz, 500,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 12 + |
integrated gpu max frequency | 766 MHz (0.766 GHz, 766,000 KHz) + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
last order | April 5, 2012 + |
last shipment | October 8, 2012 + |
ldate | September 26, 2010 + |
manufacturer | Intel + |
market segment | Mobile + |
max cpu count | 1 + |
max junction temperature | 378.15 K (105 °C, 221 °F, 680.67 °R) + |
max memory | 8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) + |
max memory bandwidth | 15.88 GiB/s (16,261.12 MiB/s, 17.051 GB/s, 17,051.02 MB/s, 0.0155 TiB/s, 0.0171 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Westmere + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | i5-560M + |
name | Intel Core i5-560M + |
package | rPGA-988A + and BGA-1288 + |
part number | BX80617I5560M +, CN80617005487AA + and CP80617005487AA + |
platform | Calpella + |
process | 32 nm (0.032 μm, 3.2e-5 mm) + |
release price | $ 225.00 (€ 202.50, £ 182.25, ¥ 23,249.25) + |
s-spec | SLBTS + and SLBTT + |
series | i5-500 + |
smp max ways | 1 + |
supported memory type | DDR3-1066 + |
tdp | 35 W (35,000 mW, 0.0469 hp, 0.035 kW) + |
technology | CMOS + |
thread count | 4 + |
transistor count | 382,000,000 + |
turbo frequency (1 core) | 3,199.99 MHz (3.2 GHz, 3,199,990 kHz) + |
turbo frequency (2 cores) | 2,933.33 MHz (2.933 GHz, 2,933,330 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |