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'''OCTEON TX''' is a family of {{arch|64}} [[multi-core]] [[ARM]] microprocessors designed by [[Cavium]] and introduced in [[2016]]. These processors are primarily marketed towards makers of network infrastructure, enterprise and data center devices. The OCTEON TX family combines the features of the {{\\|OCTEON}} family with the technology of the ThunderX processors.
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'''OCTEON TX''' is a family of {{arch|64}} [[multi-core]] [[ARM]] microprocessors designed by [[Cavium]] and introduced in [[2016]]. These processors are primarily marketed towards makers of network infrastructure, enterprise and data center devices. The OCTEON TX family combines the features of the {{\\|OCTEON}} family with the technology of the {{\\|ThunderX}} processors.
  
 
== Overview ==
 
== Overview ==

Latest revision as of 17:35, 1 February 2019

Cavium OCTEON TX
Developer Cavium
Type System on chips
Introduction May 2, 2016 (announced)
ISA ARMv8
µarch ThunderX
Word size 64 bit
8 octets
16 nibbles
Technology CMOS
Package 1676 BGA, 676 FCBGA, 555 FCBGA
Succession
OCTEON III

OCTEON TX is a family of 64-bit multi-core ARM microprocessors designed by Cavium and introduced in 2016. These processors are primarily marketed towards makers of network infrastructure, enterprise and data center devices. The OCTEON TX family combines the features of the OCTEON family with the technology of the ThunderX processors.

Overview[edit]

Members[edit]

CN80xx Series[edit]

The CN80xx series come with 2 to 4 thunderx1 cores. Running at 800-1500MHz.

CN81xx Series[edit]

The CN81xx series come with 2 to 4 thunderx1 cores. Running at 1200-2000MHz.

CN82xx Series[edit]

The CN82xx series come with 8 to 12 thunderx1 cores. Running at 1200-1800MHz.

CN83xx Series[edit]

The CN83xx series come with 8 to 24 thunderx1 cores. Running at 1500-2200MHz.

CN83xx-Series Microprocessors
CPUMemoryHardware Accelerators
ModelPriceLaunchedCoresL2$PowerFreqMem TypeMax MemECCEncryptionCompressionTCPQoS
Count: 0

Datasheet[edit]

Facts about "OCTEON TX - Cavium"
designerCavium +
first announcedMay 2, 2016 +
full page namecavium/octeon tx +
instance ofsystem on a chip family +
instruction set architectureARMv8 +
main designerCavium +
microarchitectureThunderX +
nameCavium OCTEON TX +
package1676 BGA +, 676 FCBGA + and 555 FCBGA +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +