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Difference between revisions of "cavium/microarchitectures/thunderx1"
(added rough description of original ThunderX from public sources) |
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|type=Superscalar | |type=Superscalar | ||
|type 2=Superpipeline | |type 2=Superpipeline | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
|decode=4? | |decode=4? | ||
|isa=ARMv8.1 | |isa=ARMv8.1 | ||
| Line 22: | Line 17: | ||
|l1i=78 KiB | |l1i=78 KiB | ||
|l1i per=core | |l1i per=core | ||
| − | |l1i desc= | + | |l1i desc=39-way set associative |
|l1d=32 KiB | |l1d=32 KiB | ||
|l1d per=core | |l1d per=core | ||
| − | |l1d desc= | + | |l1d desc=32-way set associative |
|l2=16 MiB | |l2=16 MiB | ||
|l2 per=socket | |l2 per=socket | ||
| − | |l2 desc= | + | |l2 desc=16-way set associative |
| + | |successor=Vulcan | ||
| + | |successor link=cavium/microarchitecture/thunderx1 | ||
}} | }} | ||
Revision as of 21:40, 3 December 2018
| Edit Values | |
| ThunderX1 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Cavium |
| Manufacturer | GlobalFoundries |
| Introduction | 2014 |
| Process | 28 nm |
| Core Configs | 24, 48 |
| Pipeline | |
| Type | Superscalar, Superpipeline |
| Decode | 4? |
| Instructions | |
| ISA | ARMv8.1 |
| Extensions | NEON, TrustZone |
| Cache | |
| L1I Cache | 78 KiB/core 39-way set associative |
| L1D Cache | 32 KiB/core 32-way set associative |
| L2 Cache | 16 MiB/socket 16-way set associative |
| Succession | |
The microarchitecture of the original custom-designed Cavium ThunderX processor might be called ThunderX1 for the purposes of this wiki. [1] [2]
Facts about "ThunderX1 - Microarchitectures - Cavium"
| codename | ThunderX1 + |
| core count | 24 + and 48 + |
| designer | Cavium + |
| first launched | 2014 + |
| full page name | cavium/microarchitectures/thunderx1 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8.1 + |
| manufacturer | GlobalFoundries + |
| microarchitecture type | CPU + |
| name | ThunderX1 + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |