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Difference between revisions of "zhongshan subor/fireflight"
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'''Z+ SoC''' is a semi-custom [[quad-core]] [[x86]] [[SoC]] designed by [[AMD]] for Zhongshan Subor for their gaming PC/consoles and introduced in mid-2018. The Z+ features four {{amd|Zen|l=arch}} cores operating at 3 GHz along with a 24-CU {{amd|vega|Radeon Vega|l=arch}} GPU operating at up to 1.3 GHz. | '''Z+ SoC''' is a semi-custom [[quad-core]] [[x86]] [[SoC]] designed by [[AMD]] for Zhongshan Subor for their gaming PC/consoles and introduced in mid-2018. The Z+ features four {{amd|Zen|l=arch}} cores operating at 3 GHz along with a 24-CU {{amd|vega|Radeon Vega|l=arch}} GPU operating at up to 1.3 GHz. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=384 KiB | ||
+ | |l1i cache=256 KiB | ||
+ | |l1i break=4x64 KiB | ||
+ | |l1i desc=4-way set associative | ||
+ | |l1d cache=128 KiB | ||
+ | |l1d break=4x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=2 MiB | ||
+ | |l2 break=4x512 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=4 MiB | ||
+ | |l3 break=1x4 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=GDDR5 | ||
+ | |frequency=1200 MHz | ||
+ | |max mem=8 GiB | ||
+ | |width=256 bit | ||
+ | |max bandwidth=143.1 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | The Z+ features a {{amd|vega|Radeon Vega|l=arch}} GPU with 24 compute units. The Compute Units operate at 1,300 MHz, each with 64 32-bit [[floating point]] [[multiply-accumulate]] units. At 1.3 GHz with 128 FLOP/cycle this chip can deliver 3.994 [[TFLOPS]] raw peak performance - about 66% the performance of the {{microsoft|Scorpio Engine}} (6 TFLOPS) and three times its predecessor. | ||
+ | |||
+ | <table class="wikitable"> | ||
+ | <tr><th colspan="2">Z+ GPU</th></tr> | ||
+ | <tr><th>Unified shaders</th><td>1536 (64 × 24 CUs)</td></tr> | ||
+ | <tr><th>[[raster operation units|ROPs]]</th><td>32</td></tr> | ||
+ | <tr><th>[[texture mapping units |TMUs]]</th><td>96</td></tr> | ||
+ | <tr><th>Peak Performance</th><td> ~4 TFLOPS (3,994,000,000,000 [[FLOPS]])</td></tr> | ||
+ | </table> | ||
+ | |||
+ | {{integrated graphics | ||
+ | | gpu = Radeon Vega | ||
+ | | device id = | ||
+ | | designer = AMD | ||
+ | | execution units = 24 | ||
+ | | unified shaders = 1536 | ||
+ | | max displays = 3 | ||
+ | | max memory = 8 GiB | ||
+ | | frequency = | ||
+ | | max frequency = 1,300 MHz | ||
+ | |||
+ | | output crt = | ||
+ | | output sdvo = | ||
+ | | output dsi = | ||
+ | | output edp = | ||
+ | | output dp = Yes | ||
+ | | output hdmi = Yes | ||
+ | | output vga = | ||
+ | | output dvi = | ||
+ | |||
+ | | directx ver = 12 | ||
+ | | vulkan ver = 1.1 | ||
+ | | opengl ver = 4.6 | ||
+ | | opencl ver = 2.0 | ||
+ | | hdmi ver = | ||
+ | | dp ver = | ||
+ | | edp ver = | ||
+ | | max res hdmi = | ||
+ | | max res hdmi freq = | ||
+ | | max res dp = | ||
+ | | max res dp freq = | ||
+ | | max res edp = | ||
+ | | max res edp freq = | ||
+ | | max res vga = | ||
+ | | max res vga freq = | ||
+ | }} | ||
+ | {{zen with vega hardware accelerated video table|col=1}} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=Yes | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=No | ||
+ | |avx512cd=No | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=No | ||
+ | |avx512dq=No | ||
+ | |avx512vl=No | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=Yes | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=Yes | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=No | ||
+ | |sst=No | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=No | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=No | ||
+ | |ht=No | ||
+ | |vpro=No | ||
+ | |vtx=No | ||
+ | |vtd=No | ||
+ | |ept=No | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |intqat=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=Yes | ||
+ | |amdv=Yes | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=Yes | ||
+ | |xfr=Yes | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=Yes | ||
+ | }} |
Revision as of 18:11, 11 August 2018
Edit Values | |
General Info | |
Microarchitecture |
Z+ SoC is a semi-custom quad-core x86 SoC designed by AMD for Zhongshan Subor for their gaming PC/consoles and introduced in mid-2018. The Z+ features four Zen cores operating at 3 GHz along with a 24-CU Radeon Vega GPU operating at up to 1.3 GHz.
Contents
Cache
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Graphics
The Z+ features a Radeon Vega GPU with 24 compute units. The Compute Units operate at 1,300 MHz, each with 64 32-bit floating point multiply-accumulate units. At 1.3 GHz with 128 FLOP/cycle this chip can deliver 3.994 TFLOPS raw peak performance - about 66% the performance of the Scorpio Engine (6 TFLOPS) and three times its predecessor.
Z+ GPU | |
---|---|
Unified shaders | 1536 (64 × 24 CUs) |
ROPs | 32 |
TMUs | 96 |
Peak Performance | ~4 TFLOPS (3,994,000,000,000 FLOPS) |
Integrated Graphics Information
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[Edit] Zen with Radeon Vega Hardware Accelerated Video Capabilities | |||||
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Codec | Encode | Decode | |||
Max FPS | @1080p | @1440p | @2160p | @1080p 4:2:0 | @2160p 4:2:0 |
MPEG-2 (H.262) | 60 FPS | N/A | |||
VC-1 | |||||
VP9 8bpc | 240 FPS | 60 FPS | |||
VP9 10bpc | |||||
MPEG-4 AVC (H.264) 8bpc | 120 FPS | 60 FPS | 30 FPS | ||
MPEG-4 AVC (H.264) 10bpc | |||||
HEVC (H.265) 8bpc | 120 FPS | 60 FPS | 30 FPS | ||
HEVC (H.265) 10bpc | |||||
JPEG/MJPEG 8bpc |
Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Facts about "FireFlight - Zhongshan Subor"
full page name | zhongshan subor/fireflight + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd extended frequency range | true + |
has amd precision boost 2 | true + |
has amd sensemi technology | true + |
has ecc memory support | false + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology +, Extended Frequency Range + and Precision Boost 2 + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | Radeon Vega + |
integrated gpu designer | AMD + |
integrated gpu execution units | 24 + |
integrated gpu max frequency | 1,300 MHz (1.3 GHz, 1,300,000 KHz) + |
integrated gpu max memory | 8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB) + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
ldate | 1900 + |
max memory bandwidth | 143.1 GiB/s (146,534.4 MiB/s, 153.652 GB/s, 153,652.455 MB/s, 0.14 TiB/s, 0.154 TB/s) + |
supported memory type | GDDR5 + |