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Difference between revisions of "intel/microarchitectures/tremont"
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| + | == Codenames == | ||
| + | {{empty section}} | ||
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| + | == Brands == | ||
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| + | == Release Dates == | ||
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| + | == Technology == | ||
| + | {{empty section}} | ||
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| + | == Architecture == | ||
| + | === Key changes from {{\\|Goldmont Plus}} === | ||
| + | {{empty section}} | ||
| + | |||
| + | ====New instructions ==== | ||
| + | Termont introduced a number of {{x86|extensions|new instructions}}: | ||
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| + | * {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush | ||
Revision as of 13:00, 4 April 2018
| Edit Values | |
| Tremont µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2018/2019 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA |
| Cores | |
| Core Names | Gemini Lake |
| Succession | |
Contents
Codenames
 |
This section is empty; you can help add the missing info by editing this page. |
Brands
| |
This section is empty; you can help add the missing info by editing this page. |
Release Dates
| |
This section is empty; you can help add the missing info by editing this page. |
Technology
| |
This section is empty; you can help add the missing info by editing this page. |
Architecture
Key changes from Goldmont Plus
| |
This section is empty; you can help add the missing info by editing this page. |
New instructions
Termont introduced a number of new instructions:
-
CLWB- Force cache line write-back without flush
Facts about "Tremont - Microarchitectures - Intel"
| codename | Tremont + |
| designer | Intel + |
| full page name | intel/microarchitectures/tremont + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tremont + |