Semiconductor & Computer Engineering
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[[IBM]] uses RAIM for their [[z/Architecture]] [[mainframes]] starting with the {{ibm|z196|l=arch}} architecture and most recently in their {{ibm|z14|l=arch}}. IBM uses [[RAID 3]]-style configuration. In those systems the memory controller unit (MCU) reserves an extra memory channel for the RAIM parity. | [[IBM]] uses RAIM for their [[z/Architecture]] [[mainframes]] starting with the {{ibm|z196|l=arch}} architecture and most recently in their {{ibm|z14|l=arch}}. IBM uses [[RAID 3]]-style configuration. In those systems the memory controller unit (MCU) reserves an extra memory channel for the RAIM parity. | ||
| − | [[Intel]] uses RAIM (although they do not call it that way) [[RAID 1]]-style configuration where memory mirroring is employed in conjunction with standard ECC. | + | [[Intel]] uses RAIM (although they do not call it that way) [[RAID 1]]-style configuration for the [[Itanium]] line (e.g. 9300 series) where memory mirroring is employed in conjunction with standard ECC. |
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Latest revision as of 20:14, 4 March 2018
Redundant Array of Independent Memory (RAIM) is memory system architecture in which memory is made redundant through the use of additional memory modules and techniques such as striping, mirroring, or parity very similar to RAID used for storage. RAIM goes beyond typical error checking such as ECC and can recover from bit, lane, and even catastrophic memory channel failures.
Implementations[edit]
IBM uses RAIM for their z/Architecture mainframes starting with the z196 architecture and most recently in their z14. IBM uses RAID 3-style configuration. In those systems the memory controller unit (MCU) reserves an extra memory channel for the RAIM parity.
Intel uses RAIM (although they do not call it that way) RAID 1-style configuration for the Itanium line (e.g. 9300 series) where memory mirroring is employed in conjunction with standard ECC.
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