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Difference between revisions of "cavium/octeon/cn3860-600bg1521-scp"
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| name = Cavium CN3860-600 SCP | | name = Cavium CN3860-600 SCP | ||
| no image = | | no image = |
Latest revision as of 16:12, 13 December 2017
Edit Values | |||||||
Cavium CN3860-600 SCP | |||||||
General Info | |||||||
Designer | Cavium | ||||||
Manufacturer | TSMC | ||||||
Model Number | CN3860-600 SCP | ||||||
Part Number | CN3860-600BG1521-SCP | ||||||
Market | Networking | ||||||
Introduction | September 13, 2004 (announced) June 1, 2005 (launched) | ||||||
General Specs | |||||||
Family | OCTEON | ||||||
Series | CN3800 | ||||||
Frequency | 600 MHz | ||||||
Microarchitecture | |||||||
ISA | MIPS64 (MIPS) | ||||||
Microarchitecture | cnMIPS | ||||||
Core Name | cnMIPS | ||||||
Process | 130 nm | ||||||
Technology | CMOS | ||||||
Word Size | 64 bit | ||||||
Cores | 16 | ||||||
Threads | 16 | ||||||
Max Memory | 16 GiB | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Packaging | |||||||
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The CN3860-600 SCP is a 64-bit hexadeca-core MIPS secure network communication microprocessor (SNP) designed by Cavium and introduced in 2005. This processor, which incorporates sixteen cnMIPS cores, operates at 600 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and encryption. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Networking[edit]
Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN3860-600 SCP - Cavium"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN3860-600 SCP - Cavium#package + |
base frequency | 600 MHz (0.6 GHz, 600,000 kHz) + |
core count | 16 + |
core name | cnMIPS + |
designer | Cavium + |
family | OCTEON + |
first announced | September 13, 2004 + |
first launched | June 1, 2005 + |
full page name | cavium/octeon/cn3860-600bg1521-scp + |
has ecc memory support | true + |
has hardware accelerators for cryptography | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
instance of | microprocessor + |
isa | MIPS64 + |
isa family | MIPS + |
l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 64-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
ldate | June 1, 2005 + |
main image | + |
manufacturer | TSMC + |
market segment | Networking + |
max cpu count | 1 + |
max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 1 + |
microarchitecture | cnMIPS + |
model number | CN3860-600 SCP + |
name | Cavium CN3860-600 SCP + |
package | FCBGA-1521 + |
part number | CN3860-600BG1521-SCP + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
series | CN3800 + |
smp max ways | 1 + |
supported memory type | DDR2-800 + |
technology | CMOS + |
thread count | 16 + |
word size | 64 bit (8 octets, 16 nibbles) + |