From WikiChip
Difference between revisions of "cavium/octeon/cn3860-600bg1521-exp"
m (Bot: corrected param) |
m (Bot: moving all {{mpu}} to {{chip}}) |
||
Line 1: | Line 1: | ||
{{cavium title|CN3860-600 EXP}} | {{cavium title|CN3860-600 EXP}} | ||
− | {{ | + | {{chip |
| name = Cavium CN3860-600 EXP | | name = Cavium CN3860-600 EXP | ||
| no image = | | no image = |
Latest revision as of 16:11, 13 December 2017
Edit Values | |||||||
Cavium CN3860-600 EXP | |||||||
![]() | |||||||
General Info | |||||||
Designer | Cavium | ||||||
Manufacturer | TSMC | ||||||
Model Number | CN3860-600 EXP | ||||||
Part Number | CN3860-600BG1521-EXP | ||||||
Market | Networking | ||||||
Introduction | August 22, 2005 (announced) August 22, 2005 (launched) | ||||||
General Specs | |||||||
Family | OCTEON | ||||||
Series | CN3800 | ||||||
Frequency | 600 MHz | ||||||
Microarchitecture | |||||||
ISA | MIPS64 (MIPS) | ||||||
Microarchitecture | cnMIPS | ||||||
Core Name | cnMIPS | ||||||
Process | 130 nm | ||||||
Technology | CMOS | ||||||
Word Size | 64 bit | ||||||
Cores | 16 | ||||||
Threads | 16 | ||||||
Max Memory | 16 GiB | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Packaging | |||||||
|
The CN3860-600 EXP is a 64-bit hexadeca-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates sixteen cnMIPS cores, operates at 600 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||
|
Memory controller[edit]
![]() |
Integrated Memory Controller
|
|||||||||||||||
|
Expansions[edit]
![]() |
Expansion Options
|
|||||||||||||||
|
Networking[edit]
![]() |
Networking
|
|||||||
|
Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
![]() |
Hardware Accelerators
|
|||||||||||||||||
|
Block diagram[edit]
Datasheet[edit]
Facts about "CN3860-600 EXP - Cavium"