Latest revision as of 15:11, 13 December 2017

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Cavium CN3850-500 NSP
General Info
Designer	Cavium
Manufacturer	TSMC
Model Number	CN3850-500 NSP
Part Number	CN3850-500BG1521-NSP
Market	Networking
Introduction	September 13, 2004 (announced) June 1, 2005 (launched)
General Specs
Family	OCTEON
Series	CN3800
Frequency	500 MHz
Microarchitecture
ISA	MIPS64 (MIPS)
Microarchitecture	cnMIPS
Core Name	cnMIPS
Process	130 nm
Technology	CMOS
Word Size	64 bit
Cores	12
Threads	12
Max Memory	16 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Packaging
Package FCBGA-1521 (BGA) Ball Count 1521 Interconnect BGA-1521

The CN3850-500 NSP is a 64-bit dodeca-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2005. This processor, which incorporates twelve cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 480 KiB 491,520 B 0.469 MiB L1I$ 384 KiB 393,216 B 0.375 MiB 12x32 KiB 64-way set associative   L1D$ 96 KiB 98,304 B 0.0938 MiB 12x8 KiB 64-way set associative Write-through L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     1x1 MiB 8-way set associative

Memory controller[edit]

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR2-800 Supports ECC Yes Max Mem 16 GiB Controllers 1 Channels 1 Width 128 bit Max Bandwidth 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s Bandwidth Single 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

	Expansion Options
	PCI-X Width 64 bit Clock 133.33 MHz Rate 1,017.25 MiB/s Features host or slave UART Ports 2 GP I/O Yes

Networking[edit]

[Edit/Modify Network Info]

	Networking
	MII RGMII Yes (Ports: 8) SPI SPI-4.2 Yes (Ports: 2)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

	Hardware Accelerators
	Encryption Hardware Implementation Yes Types DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH RegEx RegEx Yes Features 16 Engines Networking TCP Yes QoS Yes Compression Compression Yes Decompression Yes

Block diagram[edit]

Datasheet[edit]

• OCTEON CN38XX/CN36XX 4 to 16-Core Product Brief