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Revision as of 14:54, 13 December 2017

Template:mpu The Core i7-3960X Extreme Edition was a 64-bit high-end hexa-core microprocessor introduced by Intel in late 2011. The i7-3960X operates at 3.3 GHz with turbo mode of up to 3.9 GHz. Fabricated in 32 nm based on the Sandy Bridge microarchitecture, this chip supports up to 64 GiB (DDR3) of memory and has a Thermal Design Power of 130 W.

Cache

Main article: Sandy Bridge § Cache
Cache Info [Edit Values]
L1I$ 192 KiB
196,608 B
0.188 MiB
6x32 KiB 8-way set associative (per core)
L1D$ 192 KiB
196,608 B
0.188 MiB
6x32 KiB 8-way set associative (per core)
L2$ 1,536 KiB
1.5 MiB
1,572,864 B
0.00146 GiB
6x256 KiB 8-way set associative (per core)
L3$ 15 MiB
15,360 KiB
15,728,640 B
0.0146 GiB
20-way set associative (shared)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3-1066, DDR3-1333, DDR3-1600
Controllers 1
Channels 4
ECC Support No
Max bandwidth 51.2 GB/s
Max memory 64 GiB

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.00
Max Lanes40
Configsx1, x4, x8


Features

  • Note: VT-d support is only available on the C2 stepping version.

Die shot

  • 6 cores (Note: die contains 2 fused off cores)
  • 2,270,000,000 transistors
  • 20.8 mm x 20.9 mm
  • 434.72 mm²

core i7-3960x extreme edition.png

core i7-3960x extreme edition (annotated).png

See also

Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Core i7-3960X Extreme Edition - Intel#io +
has advanced vector extensionstrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology + and Extended Page Tables +
has intel enhanced speedstep technologytrue +
has intel turbo boost technology 2 0true +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description8-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description8-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l3$ description20-way set associative +
l3$ size15 MiB (15,360 KiB, 15,728,640 B, 0.0146 GiB) +
max pcie lanes40 +