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Difference between revisions of "intel/core i7ee/i7-3960x"
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Revision as of 14:54, 13 December 2017
Template:mpu The Core i7-3960X Extreme Edition was a 64-bit high-end hexa-core microprocessor introduced by Intel in late 2011. The i7-3960X operates at 3.3 GHz with turbo mode of up to 3.9 GHz. Fabricated in 32 nm based on the Sandy Bridge microarchitecture, this chip supports up to 64 GiB (DDR3) of memory and has a Thermal Design Power of 130 W.
Cache
- Main article: Sandy Bridge § Cache
Cache Info [Edit Values] | ||
L1I$ | 192 KiB 196,608 B 0.188 MiB |
6x32 KiB 8-way set associative (per core) |
L1D$ | 192 KiB 196,608 B 0.188 MiB |
6x32 KiB 8-way set associative (per core) |
L2$ | 1,536 KiB 1.5 MiB 1,572,864 B 0.00146 GiB |
6x256 KiB 8-way set associative (per core) |
L3$ | 15 MiB 15,360 KiB 15,728,640 B 0.0146 GiB |
20-way set associative (shared) |
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller | |
Type | DDR3-1066, DDR3-1333, DDR3-1600 |
Controllers | 1 |
Channels | 4 |
ECC Support | No |
Max bandwidth | 51.2 GB/s |
Max memory | 64 GiB |
Expansions
Expansion Options
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Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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- Note: VT-d support is only available on the C2 stepping version.
Die shot
- 6 cores (Note: die contains 2 fused off cores)
- 2,270,000,000 transistors
- 20.8 mm x 20.9 mm
- 434.72 mm²
See also
Facts about "Core i7-3960X Extreme Edition - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i7-3960X Extreme Edition - Intel#io + |
has advanced vector extensions | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology + and Extended Page Tables + |
has intel enhanced speedstep technology | true + |
has intel turbo boost technology 2 0 | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1d$ description | 8-way set associative + |
l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 15 MiB (15,360 KiB, 15,728,640 B, 0.0146 GiB) + |
max pcie lanes | 40 + |