Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "sun microsystems/ultrasparc/stp1030bga-167"
| Line 44: | Line 44: | ||
|l1d policy=write-through | |l1d policy=write-through | ||
}} | }} | ||
| + | |||
| + | == Documents == | ||
| + | === Datasheets === | ||
| + | * [[:File:stp1030a.pdf|UltraSPARC-I High-Performance, 167 & 200 MHz, 64-bit RISC Processor Datasheet]], October 1996 | ||
Revision as of 08:49, 28 November 2017
Template:mpu UltraSPARC-I 167MHz was a 64-bit SPARC microprocessor designed and introduced by Sun Microsystems in late 1995. This processor operates at 167 MHz and typically dissipates 28 W.
Cache
- Main article: UltraSPARC-I § Cache
In addition to the on-chip cache, this chip also required an external cache that is either 512 KiB, 1 MiB, 2 MiB, or 4 MiB with a line size of 64 bytes.
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||
|
|||||||||||||
Documents
Datasheets
Facts about "UltraSPARC-I 167MHz - Sun Microsystems"
| l1$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| l1d$ description | 16-way set associative + |
| l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |