Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "qualcomm/centriq/2460"
| Line 63: | Line 63: | ||
|bandwidth qchan=79.47 GiB/s | |bandwidth qchan=79.47 GiB/s | ||
|bandwidth hchan=119.21 GiB/s | |bandwidth hchan=119.21 GiB/s | ||
| + | }} | ||
| + | |||
| + | == Expansions == | ||
| + | {{expansions main | ||
| + | | | ||
| + | {{expansions entry | ||
| + | |type=PCIe | ||
| + | |pcie revision=3.0 | ||
| + | |pcie lanes=32 | ||
| + | |pcie config=x16 | ||
| + | |pcie config 2=x8 | ||
| + | |pcie config 3=x4 | ||
| + | }} | ||
| + | {{expansions entry | ||
| + | |type=SATA | ||
| + | |sata revision=3.0 | ||
| + | |sata ports=8 | ||
| + | }} | ||
}} | }} | ||
Revision as of 03:00, 9 November 2017
Template:mpu Centriq 2460 is a 64-bit 48-core ARM high-performance server microprocessor designed by Qualcomm and introduced in late 2017.This processor, which is based on the Falkor microarchitecture, is fabricated on Samsung's 10LPE process. The 2460 has a based frequency of 2.2 GHz with a TDP of 120 W and a turbo frequency of 2.6 GHz. This chip supports up to 768 GiB of hexa-channel DDR4-2666 memory.
Cache
- Main article: Falkor § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
|||||||||||||||||||||||||||||||||||||
Memory controller
 |
Integrated Memory Controller
|
|||||||||||||
|
||||||||||||||
Expansions
 |
Expansion Options |
|||||||
|
||||||||
Facts about "Centriq 2460 - Qualcomm"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Centriq 2460 - Qualcomm#pcie + |
| has ecc memory support | true + |
| l1$ size | 4,608 KiB (4,718,592 B, 4.5 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 3,072 KiB (3,145,728 B, 3 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
| l3$ description | 20-way set associative + |
| l3$ size | 60 MiB (61,440 KiB, 62,914,560 B, 0.0586 GiB) + |
| max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
| max memory channels | 6 + |
| max sata ports | 8 + |
| supported memory type | DDR4-2666 + |